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1. 发明专利

JPH01119828A MICROPROCESSOR 失效
公开(公告)号：JPH01119828A
公开(公告)日：1989-05-11
申请号：JP27741087
申请日：1987-11-04
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI VLSI ENG
发明人： NOGUCHI YOSHIKI , TSUCHIYA FUMIO , TSUKAMOTO TAKU , MASUMURA SHIGEKI , NAKAMURA HIDEO , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
摘要： PURPOSE:To improve the code efficiency by constructing an instruction system of a microprocessor in a byte unit in which an address operation and an operand operation of an operand are orthogonal to each other. CONSTITUTION:When an address is supplied from a microprocessor, read-out and write of a data are executed through data buses 16, 17 and among the data which are supplied through the data bus H17, an instruction code is sent to an instruction register 10 through prefetch registered 18, 19 in which a prefetched instruction code is stored, and a data for executing an arithmetic processing is inputted to an arithmetic circuit 4. The instruction code is further sent from the instruction register 10 to indirect registers 11-14 for holding an instruction data and a part of the instruction code in the course of executing an instruction. An instruction decoder 1 outputs its address to a microprogram store memory 5.

2. 发明专利

JPH0491519A PRIORITY ENCODER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING SAME 失效
公开(公告)号：JPH0491519A
公开(公告)日：1992-03-25
申请号：JP20848390
申请日：1990-08-06
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KAWAMOTO MASAMI , TSUKAMOTO TAKU
IPC分类号： G06F7/00 , G06F7/76 , G06F9/305 , H03M7/00
摘要： PURPOSE:To reduce the processing time required for retrieving the bit position of a required logical value contained in the bit strings by continuously acquiring bit positions of required logical values randomly contained in the inputted bit strings according to an operation cycle. CONSTITUTION:A bit position detection circuit 7 receives inputted bit strings Ia-Ih held by the latch circuits of flip flops 6a-6h, and prepares and outputs identification bit strings Oa-Oh which can distinguish the bit of the nearest prescribed logical value from a prescribed position from the other bits. The identification bit strings Oa-Oh are supplied to the reset terminals of the flip flops 6a-6h and identification bit strings which indicate the bit positions of prescribed logical values contained in the inputted bit strings Ia-Ih one by one are continuously outputted by the number of times corresponding to the number of bits of the prescribed logical values contained in the inputted bit strings Ia-Ih while the information held by the latch circuits are successively updated by inverting the bits held by the latch circuit corresponding to a specific bit position distinguished from the other bits.

3. 发明专利

JPS62197847A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62197847A
公开(公告)日：1987-09-01
申请号：JP3920986
申请日：1986-02-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TSUKAMOTO TAKU , TOTANI TATSURO , NAGASAKI NOBUTAKA , UJINO YOSHIAKI
IPC分类号： G11C7/00 , G06F12/16
摘要： PURPOSE:To avoid the wrong writing actions due to the program mistakes or the program runaway by storing a fact that the 1st write strobe signal from the address designation and the write control signal and inhibiting transmission of the 2nd and subsequent strobe signals based on said stored information. CONSTITUTION:A flip-flop circuit FF1 is set when the 1st write strobe signal N1 is set at a high level. Then the output N2 of the FF 1 is changed to a high level from a low level. Thus the output signal N3 of a flip-flop circuit FF2 is changed to a high level from a low level in synchronism with the timing by which the 2nd phase clock signal B is changed to a low level from a high level. The output signal of a NOR gate circuit G2 is fixed at a low level in response to the high level of the signal N3. In other words, the generation of the 1st write strobe signal W1 is inhibited regardless of the arrival of the 2nd write strobe signal N1. Then the writing action of a controller CONT is inhibited.

4. 发明专利

JPH04139562A MICROPROCESSOR OR MICROCOMPUTER PERFORMING DYNAMIC BUS CONTROL UTILIZING ADDRESS REGISTER 失效
公开(公告)号：JPH04139562A
公开(公告)日：1992-05-13
申请号：JP26058790
申请日：1990-10-01
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TSUKAMOTO TAKU
IPC分类号： G06F13/36
摘要： PURPOSE:To change the bus sizes at a high speed and with the universal applicability by designating a specific address area by a built-in register, recognizing an access given into the specific address area and switching dynamically the data bus width based on the access recognizing result. CONSTITUTION:A peripheral interface adaptor PIA 4, a floppy disk controller FDC 5, an external random access memory RAM 6, an external read-only memory ROM 7, and a direct memory access controller DMAC 8 are connected to a microcomputer 1 via an external address bus 2 and an external data bus 3. Then the system resources (PIA 4, FDC 5) having a data bus size different from that of the microcomputer 1 are built into a data processing system. In this case, the microcomputer 1 itself recognizes the presence or absence of a designated address and a specific access area and changes the bus width. Thus the bus sizes can be changed at a high speed and with the universal applicability.

5. 发明专利

JPH03156554A DATA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPH03156554A
公开(公告)日：1991-07-04
申请号：JP29557689
申请日：1989-11-14
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TSUKAMOTO TAKU , MATSUDA MAMORU
IPC分类号： G06F13/28
摘要： PURPOSE:To enable twice data transfer between respectively independent addresses with one time of a transfer request by preparing two pairs of address registers which can set a transfer source address and a transfer destination address. CONSTITUTION:When inputting a transfer request DRQ from a CPU 10 or an interruption request TIR from a timer module 21, a bus & timing control circuit 1 possesses a bus right and afterwards, codes in a register 2 for control are successively read out from the left side and decoded. At first, an address DA1 in a transfer source address register 6a is outputted onto a bus 8 and a read/write signal is asserted to a read state. Then, a device (memory 20) on the read side is accessed. Data DATA1 read out from the memory 20 are once stored through a bus 9 to a temporary register 5. A DMA controller outputs the address DA1 in a transfer destination address register 7a onto the bus 8, changes the read/write signal to a write state, accesses an I/O on the write side and outputs the data DATA1 in the register 5 onto the bus 9.

6. 发明专利

JPS6419435A DATA PROCESSOR 失效
公开(公告)号：JPS6419435A
公开(公告)日：1989-01-23
申请号：JP17470587
申请日：1987-07-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TSUKAMOTO TAKU , TSUCHIYA FUMIO
IPC分类号： G06F9/38
摘要： PURPOSE:To increase processing speed by inhibiting prefetch of instructions which are not practically executed following a branch instruction at the time of prefetching this branch instruction. CONSTITUTION:A bit DB which discriminates the branch instruction, which practically invalidates instructions prefetched following this branch instruction, from the other instructions is included in each instruction. This discrimination bit DB is directly supplied to a control means 10 from the first stage of an instruction prefetch queue 3, and the inhibition of the instruction prefetch operation of a prefetch controller 9 is controlled in accordance with this bit. Consequently, the prefetch of instructions which are not practically executed following the branch instruction is inhibited when the branch instruction is prefetched. Thus, the processing speed up to the execution of this branch instruction is increased.

7. 发明专利

JPH0443418A DATA PROCESSOR 失效
公开(公告)号：JPH0443418A
公开(公告)日：1992-02-13
申请号：JP15114490
申请日：1990-06-08
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IMAI KOJU , TSUKAMOTO TAKU
IPC分类号： G11C11/401 , G06F1/24 , G11C11/406
摘要： PURPOSE:To shorten a development period and to reduce cost by providing a register composed of a flip flop where an initial state which is set by means of a reset signal can be altered by a control signal. CONSTITUTION:The control registers CTR is composed by using a flip flop whose set state and reset state can be switched by the control signal, and the control register CTR is initialized to the different initial state by the reset signal (r) in accordance with the state of a prescribed external terminal RES. In a microcomputer incorporated in a refresh controller, for example, the control register CTR is initialized in such a way that the refresh controller executes a conventional function at a regular operation mode, and the refresh controller is prevented from functioning in a test mode. Thus, the microcomputer incorporating the refresh controller and a microcomputer which does not incorporate it and which has the same architecture can be evaluated by using the same test pattern, and cost can be reduced.

8. 发明专利

JPH0398145A MICROPROCESSOR 失效
公开(公告)号：JPH0398145A
公开(公告)日：1991-04-23
申请号：JP23544689
申请日：1989-09-11
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TSUKAMOTO TAKU
IPC分类号： G06F13/36 , G06F13/40 , G06F15/78
摘要： PURPOSE:To attain the switch of bus sizes at a high speed and with the versatile applicability by recognizing an access given to a specific address area designated by a built-in register and switching dynamically the data bus width in accordance with the recognizing result. CONSTITUTION:The registers RA and RB are assigned with the specific addresses and connected to an internal data bus DB, and a microprocessor MPU can designate the optional addresses to both registers. The address information held by the registers RA and RB are inputted to the comparators CPA and CPB, and an address signal receiving an access from the MPU is supplied to the other input of each of both comparators CPA and CPB via an internal address bus AB. The CPA and CPB transmit the levels of input signals or the coincidence signals to the MPU and identify whether or not the addresses are coincident with the specific address areas designated by the RA and RB based on the comparison output result obtained between the CPA and the CPB. This identifying result is reflected on a control signal BS and an input/output buffer IOB switches the bus width based on the signal BS. As a result, the bus sizes can be switched at a high speed and with versatile applicability.

9. 发明专利

JPS6329847A DATA PROCESSOR 失效
公开(公告)号：JPS6329847A
公开(公告)日：1988-02-08
申请号：JP17167686
申请日：1986-07-23
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TSUKAMOTO TAKU , KIMURA SADAO
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To attain rapid switching of a general register bank by forming a bank identification area storing bank identification data for specifying plural general register banks which can be switched and used in a program counter. CONSTITUTION:The bank identification (ID) area Ebr storing the bank ID data for selecting a prescribed register bank out of the register banks RB1-RB8 is formed in the program counter PC and the bank ID data are included in vectors stored in the program counter PC. Since the register bank an be switched only through vectoring of the program counter PC, a memory cycle is required only at the time of receding the program counter PC, the number of processing steps can be reduced and the switching of the register bank can be rapidly executed. Consequently, multi-task processing based upon interruption can be rapidly attained.

10. 发明专利

JPS62249217A COMPUTER SYSTEM 失效
公开(公告)号：JPS62249217A
公开(公告)日：1987-10-30
申请号：JP9219486
申请日：1986-04-23
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TSUKAMOTO TAKU , KONO TATSUHIKO
IPC分类号： G06F1/08 , G06F1/04
摘要： PURPOSE:To connect plural processors, or peripheral units having different processing speeds, by providing a circuit to frequency-divide an input clock signal, and a clock selection circuit. CONSTITUTION:The input clock signal is supplied from the clock output terminal CO of a microprocessor MPU that becomes a host computer, to the clock input terminal C1 of a peripheral unit PDU. When the PDU is operated asynchronously and independently from the MPU, a crystal oscillator Xta1 is connected. The input clock signal inputted to the terminal C1, is supplied to a clock generation circuit CG, and the circuit CG performs the waveform arrangement of the input clock signal, and forms a fundamental clock signal. The fundamental clock signal is inputted to a 1/2 frequency-dividing circuit 1/2CD, then a 1/2 frequency-dividing clock signal is formed. The fundamental clock signal, and the 1/2 frequency-dividing clock signal are selected respectively through each of switches Q1 and Q2, and they are supplied to an internal device as internal clock signals CP, and also, they are supplied to an external device through a clock output terminal C3.

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