专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH06150023A MICROCOMPUTER AND SYSTEM THEREOF 失效
公开(公告)号：JPH06150023A
公开(公告)日：1994-05-31
申请号：JP32259892
申请日：1992-11-06
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , FUKADA KAORU , WATABE MITSURU , NOGUCHI YOSHIKI , MATSUBARA KIYOSHI , MOCHIZUKI ISAMU , SUZUKAWA KAZUFUMI , MASUMURA SHIGEKI , AKAO YASUSHI , SAKAKIBARA EIJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
摘要： PURPOSE:To flexibly deal with required system construction by adopting an interface for a dynamic RAM and an interface for a memory such as a static RAM and a peripheral circuit to the microcomputer. CONSTITUTION:This microcomputer is provided with strobe signal output terminals CASH, CASL and RAS for the dynamic RAM and chip select signal output terminals CSO-CS6 for outputting chip select signals parallelly to respective outputs. Then, an address output terminal can output non-multiplexed address signals or address signals multiplexed as needed, and the input/output terminal of data is provided for selectively outputting the address signals so as to cope with the multibus system interface. Thus, the interface for the dynamic RAM and the interface for the memory such as the static RAM and the other peripheral circuit are adopted to the microcomputer.

2. 发明专利

JPH07115351A DELAYING CIRCUIT, SIGNAL PROCESSING CIRCUIT USING THE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCORPORATED WITH THE SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH07115351A
公开(公告)日：1995-05-02
申请号：JP26049493
申请日：1993-10-19
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI , URIMORI MASAHIKO , SHINAGAWA YUTAKA
IPC分类号： G11C11/407 , G11C11/4076 , H03H11/26 , H03K5/13
摘要： PURPOSE:To provide the delaying circuit technique small in layout area is and capable of constituting with a simple circuit and comparatively stably controlling the delay amount with respect to the fluctuation of power voltage and temperature, and the dispersion of manufacturing process. CONSTITUTION:This delaying circuit formed on single semiconductor substrate to be constituted with an integrated circuit of MOS structure is constituted of an NMOS transistor TRn utilizing a MOS type transistor and a capacitor C connected in series to this NMOS transistor TRn, and is connected with NOT gates NOTin, NOTout in the input and output sides. This delaying circuit utilizes an effect obtained by forming the NMOS transistor TRn and the capacitor C by the MOS structure, and is used for a signal processing circuit of the semiconductor integrated circuit device such as a pulse width adjusting circuit, a two-phase clock generating circuit, an output buffer circuit, an internal bus driver circuit and a voltage control oscillation circuit which are influenced by a fluctuation of a delay amount caused by a delay time.

3. 发明专利

JPH07264061A PLL OSCILLATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING IT 失效
公开(公告)号：JPH07264061A
公开(公告)日：1995-10-13
申请号：JP5347594
申请日：1994-03-24
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI , URIMORI MASAHIKO , UCHIYAMA TOMOHIRO , MATSUBARA KIYOSHI
IPC分类号： G06F1/04 , H03L7/099
摘要： PURPOSE:To provide a PLL oscillation circuit technique capable of preventing a malfunction and a destruction and making the circuit widely stable in oscillation and low in power consumption by detecting a control voltage to be inputted into a VCO, feedbacking this voltage to the VCO and fixing an output level. CONSTITUTION:This PLL oscillation circuit is incorporated into a semiconductor integrated circuit device such as a single chip microcomputer, and is constituted of a phase comparator 1 comparing the frequencies of an input signal and a feedback signal, a charge pump/low pass filter 2 eliminating high frequency noise components by converting them into the voltage according to the difference of the frequencies and a VCO 3 by which an oscillation frequency changes according to inputs and a voltage detection circuit 4 detecting the voltage level to be inputted in the VCO 3 and controlling the output of the VCO 3. When the error voltage to be detected by this voltage detection circuit 4 deviates from the corresponded voltage within the range of the allowable frequency of an input signal, the output of the VCO 3 is controlled and an output voltage level is fixed.

4. 发明专利

JPH06303134A PLL CIRCUIT 失效
公开(公告)号：JPH06303134A
公开(公告)日：1994-10-28
申请号：JP11226793
申请日：1993-04-15
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI , KUCHIKI TAKAYUKI
IPC分类号： G06F15/78 , G06F1/08 , H03L7/18
摘要： PURPOSE:To extend the available frequency of the PLL circuit by providing plural VCOs whose output frequency characteristic with respect to a control voltage differs and validating their output signals alternatively according to a prescribed selection control signal. CONSTITUTION:An oscillation circuit OSC applies an input clock signal CO to a phase comparator circuit PFC of the PLL circuit. A clock shaping circuit CT delays and shapes the clock signal CD from a frequency divider circuit FD1 to generate n-phase system clock signals CP1-CPn, which are fed to a microcomputer. A control voltage VC is fed in common to VCOs 1-3 via an LPF and a corresponding selection signal is fed through external terminals CM1-CM3. The terminals CM 1-3 are coupled with a power supply voltage VCC of the circuit alternatively depending on the frequency of the signals CP 1-CPn. Thus, the available frequency of the microcomputer is extended.

5. 发明专利

JPH05343919A 失效
公开(公告)号：JPH05343919A
公开(公告)日：1993-12-24
申请号：JP17204492
申请日：1992-06-06
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI
IPC分类号： H03B5/32
摘要： PURPOSE:To reduce the required layout area and to make the operation stable for an oscillation circuit built in a microcomputer or the like. CONSTITUTION:In a microcomputer MC where an oscillation circuit OSC is built in, a crystal oscillator XO is mounted externally and external terminals XTAL and EXTAL are provided, the output of an inverter INV1 is coupled with the terminal EXTAL and acts like a static electricity protection element. Moreover, both transistors(TRs) PM1, NM1 being components of the INV1 are arranged closely and symmetrically to a bonding pad PEXTAL corresponding to the terminal EXTAL. Moreover, a feedback resistor Rf provided between an input terminal and an output terminal of the INV1 and TRs PM2, PM3 and NM2, NM3 being components of the inverter INV2 transmitting its output signal to a post-stage circuit are arranged closely and symmetrically to the TRs PM1, NM1.

6. 发明专利

JPH0728553A CLOCK GENERATING CIRCUIT AND DATA PROCESSOR 失效
公开(公告)号：JPH0728553A
公开(公告)日：1995-01-31
申请号：JP19551293
申请日：1993-07-13
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI , KUCHIKI TAKAYUKI , MATSUBARA KIYOSHI
IPC分类号： G06F1/10 , G06F1/06 , G06F15/78
摘要： PURPOSE:To provide the technique which suppresses the variance of the non- overlap time. CONSTITUTION:A first circuit 10A which takes in a clock to generate a first clock, an inverting circuit INV3 which inverts the clock, and a second circuit 10B which takes in the inverted output to generate a second clock are provided, and a delay circuit 6 which delays the inputted clock and a delay extent control circuit 7 which controls charging/discharging of a capacitor through a constant current source to control the extent of delay of the delay circuit 6 are included to form first and second circuits, thereby reducing the dependency upon the supply voltage and the temperature variance of the clock circuit.

7. 发明专利

JPH06168344A DATA PROCESSOR 失效
公开(公告)号：JPH06168344A
公开(公告)日：1994-06-14
申请号：JP28136992
申请日：1992-10-20
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI , KUCHIKI TAKAYUKI , ABE HIROSHI , MATSUBARA KIYOSHI , YAMAZAKI TAKANAGA
IPC分类号： G06F1/04 , G06F15/78
摘要： PURPOSE:To provide a clock generating circuit included in a single chip microcomputer appropriate for high-speed operation, low power consumption operation and low voltage operation. CONSTITUTION:The single chip microcomputer is provided with an oscillation circuit 31, a clock generating circuit 33 for generating a clock having the same frequency as that of an output from the circuit 31 and about 50% duty and a control circuit 32 capable of stopping both the circuits 31, 33 by executing an instruction. Since the oscillation frequency of the circuit 31 is the same as the clock frequency of clocks to be supplied to respective modules in the single chip microcomputer, internal operation frequency can be increased without using an oscillator with high frequency. Since an internal clock with high frequency and the circuit 31 can be stopped by an instruction, power consumption can be reduced.

8. 发明专利

JPH07105173A DATA PROCESSOR 失效
公开(公告)号：JPH07105173A
公开(公告)日：1995-04-21
申请号：JP24426593
申请日：1993-09-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SUZUKAWA KAZUFUMI , ITOU YOSHITAKA , HASEGAWA ATSUSHI , HAYAKAWA AKIO , HAYASAKA TOSHIMI
IPC分类号： G11C11/407 , G06F1/08 , G06F12/00 , G06F15/78
摘要： PURPOSE:To obtain a single-chip microcomputer-incorporated type clock oscillation circuit which generates a clock facilitating easily interfacing a synchronous DRAM by generating clock pulses which are out of phase with clock pulses of a single-chip microcomputer and interfacing the synchronous DRAM. CONSTITUTION:A clock pulse generator CPG21 can select clock modes 0-6 according to combinations of three clock mode terminals MD0-MD2. When the clock modes 0 to are selected, clocks which has cycles equal to, and twice and four times as long as those of an inputted clock can be used as an internal clock by a PLL circuit 212. In, for example, the test mode 1, the external clock is inputted to the PLL circuit 212 from an input terminal EXTAL and its output is inputted to a PLL circuit 213, which is put in operation in 90 deg. out-of-phase relation with the input clock. At this time, a clock which is inputted from an input/output terminal CK10 to the PLL circuit 213 is outputted.

9. 发明专利

JPH06119469A EMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06119469A
公开(公告)日：1994-04-28
申请号：JP28660292
申请日：1992-10-01
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： HASHIMOTO KOICHIRO , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , TOTANI TATSURO , SHIBUKAWA YOSHIMICHI
IPC分类号： G06F15/78 , H01L21/8246 , H01L27/112
摘要： PURPOSE:To prevent information obtd. from an initial user from being leaked while reducing the cost of a microcomputer or the like by providing the semiconductor device of the single chip microcomputer or the like capable of turning a built-in mask ROM to a use disable state without performing any bonding processing. CONSTITUTION:The activating part ROMS of a read only memory ROM composed of a mask ROM is provided with a start control MOSFETCN 1 for selectively changing the threshold voltage by selectively performing ion injection after a protection film at least the upper part of the channel is partially removed or thinned previously and the protection film is formed. By selectively turning on this start control MOSFETCN 1, a start control signal ROME to the read only memory ROM is selectively made invalid.

10. 发明专利

JP2000331489A SEMICONDUCTOR DEVICE AND MICROCOMPUTER 失效
公开(公告)号：JP2000331489A
公开(公告)日：2000-11-30
申请号：JP13658799
申请日：1999-05-18
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TANAKA TOSHIHIRO , SHINAGAWA YUTAKA , SUZUKAWA KAZUFUMI , FUJITO MASAMICHI , KAWAI YOZO
IPC分类号： G11C16/06 , G05F1/56
摘要： PROBLEM TO BE SOLVED: To reduce ripple of boosting voltage without increasing a layout area of a boosting power source circuit by controlling clock supply operation based on boosting voltage of plural charge pump circuits to which clock signals of which phases are different respectively are supplied. SOLUTION: Plural charge pump circuits 2, 3, 4 inputs power source voltage Vcc synchronizing with clock signals P1, P2, P3 respectively, performs boosting operation, and outputs it to a common connection node Nout. A ring oscillator 5 supplies clock signals P1, P2, P3 having different phases respectively to the plural charge pump circuits 2, 3, 4. Also, a resistor voltage dividing circuit 7 and a comparing circuit 6 constitute a control circuit controlling operation in which clock signals P1, P2. P3 are supplied to the plural charge pump circuits 2, 3, 4 from the ring oscillator 5 based on boosting voltage formed by plural charge pump circuits 2, 3, 4.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式