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1. 发明专利

JPS615523A METHOD OF DRY ETCHING 失效
公开(公告)号：JPS615523A
公开(公告)日：1986-01-11
申请号：JP12524884
申请日：1984-06-20
申请人： HITACHI LTD , HITACHI IRUMA DENSHI KK , HITACHI MICROCUMPUTER ENG
发明人： MIYAZAKI MASARU , YASUDA TAKESHI , MASUKI JIYUNJI , HASHIMOTO TETSUKAZU
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3213
摘要： PURPOSE:To machine a high melting point metal in a directional property without damaging a GaAs substrate by using NF3 gas for reactive gas in the step of ultrafinely machining the metal formed on a compound semiconductor by a reactive ion etching method. CONSTITUTION:NF3 gas is used for reactive gas in the step of ultrafinely machining a high melting point metal formed on a compound semiconductor by a reactive ion etching method. For example, tungsten silicide 2 is coated by sputtering on a crystal formed with an N type active layer 10 on a semi-insulating GaAs substrate 1. A gate pattern 20 of the desired size is formed of photoresist, a tungsten silicide 3 is machined by reactive ion etching method using mixture gas of NF3 gas and N2 with it as a mask. Thus, since the metal can be machined with good controllability without damaging the GaAs, an integrated circuit using GaAs semiconductor can be performed in high performance.

2. 发明专利

JPS59224548A APPARATUS FOR SURFACE ANALYSIS 失效
公开(公告)号：JPS59224548A
公开(公告)日：1984-12-17
申请号：JP9779083
申请日：1983-06-03
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YANAGISAWA HIROSHI , SUZUKI YOSHISHIGE , SUZUKI MICHIO , HASHIMOTO TETSUKAZU , OOHAYASHI HIDEHITO
IPC分类号： H01J37/252 , G01N1/34 , G01N1/40 , G01N23/22
摘要： PURPOSE:To obtain the titled apparatus having a mechamism for removing effectively only a contamination of an organic material adhering to a sample surface by providing a mercury-arc lamp of low pressure at a position opposed to the sample in a vacuum vessel, and providing a mechanism capable of supplying an oxygen to the sample surface. CONSTITUTION:The mercury-arc lamp 12 of low pressure and a nozzle 13 for supplying oxygen are provided at the position opposed to an analyzing sample 11. The sample 11 is attached to a sample base 14 in accordance with usual operation, an inner part of an analyzing chamber is evacuated, then, the lamp 12 is lit to irradiate ultraviolet ray to the surface of the sample 11, and the oxygen is leaked from the nozzle 13 by only a very small quantity to supply the oxygen to the surface of the sample 11. By this operation, ozone is generated near the surface of the sample 11, thereby, the organic contamination material at the sample surface is removed. After treating said surface in such a way only for 3min, the oxygen is stopped and the lamp 12 is turned off, the vacuum evacuation is performed successively for 20min, then the sample 1 is analyzed continuously.

3. 发明专利

JPS6252470B2 失效
公开(公告)号：JPS6252470B2
公开(公告)日：1987-11-05
申请号：JP2348578
申请日：1978-03-03
申请人： HITACHI LTD
发明人： YOSHIDA ISAO , YAMAGUCHI KEN , OKABE TAKEAKI , MASUHARA TOSHIAKI , SAKAI YOSHIO , KOYANAGI MITSUMASA , OCHI SHIKAYUKI , ITO HIDESHI , NAGATA MINORU , HASHIMOTO TETSUKAZU
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417

4. 发明专利

JPS6298672A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6298672A
公开(公告)日：1987-05-08
申请号：JP23734385
申请日：1985-10-25
申请人： HITACHI LTD
发明人： HATTA YASUSHI , MITSUSADA KAZUMICHI , TANAKA HIRONORI , SHIGETA JUNJI , MATSUNAGA NOBUTOSHI , KODERA NOBUO , HASHIMOTO TETSUKAZU
IPC分类号： H01L27/088 , H01L21/337 , H01L21/338 , H01L21/8236 , H01L27/06 , H01L29/80 , H01L29/808 , H01L29/812
摘要： PURPOSE:To prevent the change of the power consumption of a field effect transistor or reduce power consumption thereof by setting the field effect transistor controlling currents by the elongation of a depletion layer so that drain currents are not altered or drain currents are minimized even when a junction temperature is elevated. CONSTITUTION:An inverter circuit is constituted of a depletion type (D type) MESFET Qd and an enhancement type (E type) MESFET Qe. the MESFET Qd is composed of an n-type semiconductor region 2A in low concentration, a gate electrode 3 shaped to the main surface of the region 2A and a pair of n type semiconductor regions 4 in high concentration continuously formed to the semiconductor region 2A. The MESFET Qe is organized by an n-type semiconductor region 2B in low concentration, a gate electrode 3 shaped to the main surface of the region 2B and a pair of n type semiconductor regions 4 in high concentration connected to the semiconductor region 2B. The MESFET Qd for the inverter circuit is constituted of threshold voltage Vth where drain currents Ids (currents flowing between a source and a drain in the MESFET Qd) do not alter or reduce even when a junction temperature Tj is elevated.

5. 发明专利

JPS6254966A SCHOTTKY GATE FIELD EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6254966A
公开(公告)日：1987-03-10
申请号：JP19384185
申请日：1985-09-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAMIYANAGI KIICHI , MIYAZAKI MASARU , KOBAYASHI MASAYOSHI , KAYAMA SATOSHI , KODERA NOBUO , SHIGETA JUNJI , YANAGISAWA HIROSHI , HASHIMOTO TETSUKAZU , MASUKI JIYUNJI , ISOBE YOSHIHIKO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/08
摘要： PURPOSE:To obtain a short gate MESFET having high performance by disposing the second source and drain regions having lower carrier density than the first source and drain regions between a gate electrode, and the first source region and the drain region respectively. CONSTITUTION:Source and drain regions are formed double and to be self- aligned with a gate electrode, the second source and drain regions 14, 14' of the gate electrode 3 side have relatively low carrier density and shallow depth, the first source and drain regions 4, 4' of the side separated from the gate electrode have high carrier density to form a high performance MESFET having small short channel effect, and low source resistance. The regions 14, 14' are formed by ion implanting at 15 with the electrode 3 as a mask, and the regions 4, 4' of higher carrier density than the regions 14, 14' are separated from the electrode 3 by ion implanting at 9 with the side wall 16 formed on the side of the electrode 3 as a mask. Thus, a high performance MESFET is obtained.

6. 发明专利

JPS6118340B2 JPS6118340B2 - 失效
公开(公告)号：JPS6118340B2
公开(公告)日：1986-05-12
申请号：JP11471976
申请日：1976-09-27
申请人： Hitachi Ltd
发明人： MASUHARA TOSHIAKI , SUNAMI HIDEO , KAMIGAKI YOSHIAKI , HASHIMOTO TETSUKAZU
IPC分类号： H01L27/10 , H01L21/768 , H01L21/82 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805

7. 发明专利

JPS60149159A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60149159A
公开(公告)日：1985-08-06
申请号：JP11638084
申请日：1984-06-08
申请人： HITACHI LTD
发明人： HORI RIYOUICHI , KUBO SEIJI , HASHIMOTO TETSUKAZU , NISHIMATSU SHIGERU , ITOU KIYOO
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE:To easily obtain the memory device increased in integration by a method wherein the device is put in a multilayer structure by opening the window of part of the electrode of a semiconductor circuit element provided in or on a semiconductor substrate both through the same insulation film. CONSTITUTION:A P type Si substrate 1 is isolated with oxide films 2, and phosphorus- doped poly Si gate electrodes 6a and 6b are provided on gate oxide films 4 and coated with thermal oxide films 5a, 5b, 8a, and 8b. Windows are opened 12 and 11b through the oxide films 5b and 8a, and the windows are selectively filled with phosphorus-doped poly Si layers 7b and 7c, respectively. Next, on thermal diffusion of N-layeres 3a-3d after etch-removal of the oxide films 5a and 5b, the N-layer 3b generates by diffusion from the layer 7b and connects with layer 3c; accordingly, the drain of an FET is obtained, and the N-layer 3a serves as the source of a switching FET. The whole is covered with PSG's 9a-9d, and windows are selectively opened; then, Al wirings 10 are attached, resulting in completion. This construction allows no difference in shape because respective windows 11a-11c are processed in the same insulation film, and no variation in shape at the time of window opening in different-quality insulation films 9 because of previous removal of the film 5a in the window 11b. Therefore, the memory device can be obtained without the decrease in integration degree, yield, or performance.

8. 发明专利

JPS6032974B2 失效
公开(公告)号：JPS6032974B2
公开(公告)日：1985-07-31
申请号：JP2797877
申请日：1977-03-16
申请人： HITACHI LTD
发明人： TANIDA JUJI , HASHIMOTO TETSUKAZU
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/316

9. 发明专利

JPS6035566A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6035566A
公开(公告)日：1985-02-23
申请号：JP12172584
申请日：1984-06-15
申请人： HITACHI LTD
发明人： SAKAI YOSHIO , KOYANAGI MITSUMASA , SUNAMI HIDEO , HASHIMOTO TETSUKAZU
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE:To increase both of the integration density of an MOS-RAM memory cell and the accumulated capacitance by a method wherein an aperture the first insulation film has is filled with the first conductive film, further the second insulation film is formed by lamination so that at least part of the surface of the first conductive film may be exposed, thereafter the second conductive film if formed. CONSTITUTION:A thin oxide film 33 is formed on the surface of an Si substrate 30, and thereafter boron ions B are implanted to the Si substrate 30 with a photo resist mask 34 as a mask, resulting in the formation of a p layer 35. Next, the film 34 is removed after etching of the oxide film 33 with the film 34 as a mask, the polycrystalline Si 36 of the first layer doped with a high concentration n type impurity being deposited, and next an insulation film 38 of high dielectric constant being deposited on the polycrystalline Si. Then, the insulation film 38 and the Si 36 are etched by the method of plasma etching at the same time. Thereafter, the polycrystalline Si 39 of the second layer containing a high concentration n type impurity is deposited, and the pattern is formed by photo etching so as to cover the film 38. The oxide film 33 is removed, and a thin gate oxide film 40 is formed.

10. 发明专利

JPS59225131A PREPARATION OF DIFLUOROMETHANE 失效
公开(公告)号：JPS59225131A
公开(公告)日：1984-12-18
申请号：JP10046483
申请日：1983-06-06
申请人： SHOWA DENKO KK , HITACHI LTD
发明人： TAKAYAMA SHIGERU , TAKAICHI AKIRA , NAKAYAMA HIDETOSHI , KAWASAKI HIROAKI , HASHIMOTO TETSUKAZU
IPC分类号： C07C17/20 , B01J27/00 , C07B61/00 , C07C17/00 , C07C19/08 , C07C67/00
摘要： PURPOSE:To obtain the titled substance economically in high yield, by subjecting dishloromethane and HF to gaseous-phase reaction at a specific temperature in the presence of a catalyst consisting of chromium fluoride or obtained by mixing chromium fluoride with a carrier followed by molding the blend, or supporting it on the carrier. CONSTITUTION:CH2Cl2 is reacted with HF in a gaseous phase at 200-500 deg.C (preferably at 300-450 deg.C) in the presence of a catalyst consisting of chromium fluoride or obtained by blending it with a carrier(e.g., active carbon) followed by molding, or supporting it on the carrier, to give the titled substance. CrF3 is used as chromium fluoride, or it is obtained by fluorinating a chrominum compound(e.g., chromium oxide, chromium hydroxide, chromium chloride) and used, and, when the compound contains a chromiun compound except CrF3, it is necessary to fluorinate the compound after molding or supporting on the carrier.

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