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1. 发明专利

JPH04127441A INVERTER CIRCUIT 失效
公开(公告)号：JPH04127441A
公开(公告)日：1992-04-28
申请号：JP24707290
申请日：1990-09-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , YAZAWA MASAMITSU , MIYAZAKI MASARU
IPC分类号： H01L29/73 , H01L21/331 , H01L21/338 , H01L29/737 , H01L29/778 , H01L29/78 , H01L29/812 , H03K19/02
摘要： PURPOSE:To manufacture a small-sized resistance element without being subjected to a restriction on a fine processing technique, to largely reduce the area occupied by an inverter circuit and to enhance the integration density of the circuit by a method wherein a resistor composed of a semiconductor whisker is utilized as the load element of the inverter circuit. CONSTITUTION:Since a whisker is grown only in a direction which is equivalent to 111, the growth direction of the whisker is different depending on the plane orientation of a substrate crystal. In the case of a 100-plane substrate, a whisker 1 is stretched to a direction of 45 deg.. In the case of a 111-plane substrate, the substrate 1 is stretched vertically from a high-concentration conductive layer 4. In the case of a 110-plane, the whisker 1 is stretched to a direction of 45 deg.. The whisker 1 is formed of GaAs doped with impurity Si or the like. In order to reduce a contact resistance, it is possible to use Ge which has been doped with a compound semiconductor such as InAs, InGaAs or the like whose band gap is small or with impurities (phosphorus or the like).

2. 发明专利

JPH1079471A SEMICONDUCTOR DEVICE, ITS MANUFACTURE AND FLEXIBLE CARD 失效
公开(公告)号：JPH1079471A
公开(公告)日：1998-03-24
申请号：JP23501696
申请日：1996-09-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYAZAKI MASARU , ODA HIROTO , OTA HIROSHI , USAMI MITSUO
IPC分类号： G06K19/07 , G06K19/077 , H01L21/304 , H01L21/822 , H01L25/04 , H01L25/18 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To increase yield by dividing at least one of the layers forming a device on a semiconductor substrate having a thickness within a specific range and connecting the divided devices in parallel. SOLUTION: A cell structure is formed by dividing Ti-Pt lower electrode layer 43 and a BST high dielectric layer 44, and a Ti-Pt-Au upper electrode layer 45, formed on an SiO2 layer 2 on an Si monocrystal substrate 1, into cells. An MIM-type structure is formed on the entire wafer surface, and then the upper electrode layer 45 is removed and divided by ion milling with a photoresist layer as a mask. Next, an SiO2 insulating film 46 is formed on the surface, and then conduction holes connecting the upper electrode layer 45 to the lower electrode layer 43 are formed, and wiring layers 47 and 48 are formed. The divided cells are connected in parallel to each other with the wiring layers 47 and 48, thus constructing a large capacity capacitor. The Si is grind-removed from the rear surface side of the Si monocrystal substrate 1, and the substrate is etched with a chemical etchant to have a thickness of 1-100μm.

3. 发明专利

JPH0283953A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0283953A
公开(公告)日：1990-03-26
申请号：JP23505688
申请日：1988-09-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAYAMA SATOSHI , MIYAZAKI MASARU , KODERA NOBUO
IPC分类号： H01L21/768 , H01L23/522 , H01L27/095
摘要： PURPOSE:To reduce capacity between wires as well as in reference to the ground and speed up an integrated circuit by placing a dummy wire with a floating potential below a signal transmission wire at a distance shorter than the space between wires. CONSTITUTION:A wiring conductor 1 is provided on a relatively thick insulation substrate 3 with a ground conductor 3 on the rear surface and is connected to an electrode 8 of a gate and a drain of FET within an integrated circuit at a contact part 7. Then, the neighboring wire becomes a transmission channel of different signals. A dummy wire 2 with a floating potential insulated by an insulation thin film 4 is provided below this signal wire 1 and the area between the wire 1 and the dummy wire 2 is formed smaller than the gap of the wire 1. Thus, an electric line of force centered between wires is directed toward the conductor and is terminated at it and electric line of force toward the neighboring wire through the substrate G is made smaller. It reduces capacity between wires as well as in reference to the ground and speeds up an integrated circuit.

4. 发明专利

JPH01309351A SEMICONDUCTOR CHIP 失效
公开(公告)号：JPH01309351A
公开(公告)日：1989-12-13
申请号：JP13934188
申请日：1988-06-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAWADA YUKIHIRO , KAYAMA SATOSHI , MIYAZAKI MASARU , KITAMURA KEIICHI
IPC分类号： H01L27/04 , H01L21/301 , H01L21/31 , H01L21/78 , H01L21/822
摘要： PURPOSE:To prevent the progress of the exfoliation of insulating film layers by a method wherein, apart from a scribing line, a groove used to separate the insulating film layers of phosphosilicate glass, an SiO2 film and the like at a desired part on a semiconductor substrate is formed on the substrate. CONSTITUTION:Bonding pads 3 are arranged around a circuit region 4; their peripheral part is surrounded by a groove 1; in addition, its periphery is constituted as a scribing line 2. Then, when a wafer is scribed or when a chip taken out by a scribing operation is handled, it is possible to prevent that insulating film layers such as a passivating film 9, a first interlayer insulating film 7, a second interlayer insulating film 8, a protective film 10 and the like are stripped off thanks to the groove 1. By this setup, it is possible to prevent that an exfoliation of the insulating film layers progresses.

5. 发明专利

JPH01189144A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01189144A
公开(公告)日：1989-07-28
申请号：JP1253188
申请日：1988-01-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISOBE YOSHIHIKO , MIYAZAKI MASARU , TAKAHASHI JUN
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To prevent occurrence of disconnection in a multilayer interconnection, by forming a side wall comprising wiring metal on the side surface of a contact hole. CONSTITUTION:A first wiring layer 1 is formed, an interlayer insulating film 2 is deposited and a contact hole is formed. These steps are all performed by ordinary methods. Thereafter, a side wall 3 comprising wiring metal is formed on the side surface of each contact hole. Then, a second wiring layer 4 is formed, and the double-layer interconnect ion is formed. In this way, occurrence of poor conduction between the wiring layer 1 and the wring layer 4 can be prevented.

6. 发明专利

JPS6292356A CAPACITIVE DIODE FOR GAAS LSI 失效
公开(公告)号：JPS6292356A
公开(公告)日：1987-04-27
申请号：JP23122685
申请日：1985-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KODERA NOBUO , MATSUNAGA NOBUTOSHI , MIYAZAKI MASARU , KAYAMA SATOSHI , KAMIYANAGI KIICHI , SHIGETA JUNJI , TANAKA HIRONORI
IPC分类号： H01L27/04 , H01L21/338 , H01L21/822 , H01L27/06 , H01L29/812 , H01L29/93
摘要： PURPOSE:To increase the operating upper-limit voltage (withstanding voltage) of a capacitive diode used in a GaAs LSI largely by dividing a high-concentration N channel into two sections and arranging a low-concentration N channel into a configuration that the hihg-concentration N channel is connected to a section where the end surface of a gate electrode is positioned by the low-concentration N channel. CONSTITUTION:When a high-concentration N channel is brought into contact closely with a section just under a gate electrode 1 and biassed so that negative potential is applied to a terminal, currents concentrate to the end surface of the gate electrode 1. A remarkably high electric field caused by a Schottky barrier appears on the end surface of the electrode where currents concentrate. Consequently, the high- concentration N channel is divided into two section i.e. 21 and 22, and a low- concentration N channel 3 is disposed to a section where the end surface of the gate electrode 1 is positioned to a shape that the two sections 21, 22 are connected with each other. An ohmic electrode metal is connected to the low-concentration N channel 3, the ohmic electrode metal is held as one terminal at positive potential, and an end-section boundary line on the ohmic electrode side of a gate metal is positioned onto the surface of an N channel region.

7. 发明专利

JPS61287245A MULTILAYER INTERCONNECTION METHOD 失效
公开(公告)号：JPS61287245A
公开(公告)日：1986-12-17
申请号：JP12820185
申请日：1985-06-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYAZAKI MASARU , ISOBE YOSHIHIKO , MASUKI JIYUNJI , YANAGISAWA HIROSHI
IPC分类号： H01L21/3205
摘要： PURPOSE:To obtain flat multilayer interconnection by forming a photoresist spacer near a wiring pattern, rotatably coating a photoresist, etching back it to uniformly cut a raised portion with good controllability. CONSTITUTION:A PSG 30 is coated approx. 1.5mum thick on a wiring layer 20 of approx. 1mum thick on a GaAs substrate 10. A resist spacer 80 of approx. 7mum thick is formed by photocomposing technique by avoiding on the layer 20, and a projection of an interval l 2mum is formed on the entire surface of a wafer. Then, a photoresist 85 is rotatably coated, and uniformly buried. Then, a photoresist and a PSG are etched at 900 at substantially equal speed with mixture gas of CF4+O2, and projections 35 of the PSG are simultaneously exposed. A light emitting spectrum of SiO2 is altered at the moment. Thereafter, when the PSG is etched back at approx. 800nm only for the prescribed time and the resist is removed, a step B is reduced by approx. 200nm, and a step C is restricted to the value of 200nm. Thereafter, a window 60 is opened to provide he second wiring 70. According to this construction, multilayer interconnections are formed efficiently with good yield.

8. 发明专利

JPH08172161A INDUCTOR ELEMENT AND ITS MANUFACTURE AND MONOLITHIC MICROWAVE INTEGRATED CIRCUIT USING THE SAME 失效
公开(公告)号：JPH08172161A
公开(公告)日：1996-07-02
申请号：JP31363594
申请日：1994-12-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MORI MITSUHIRO , MIYAZAKI MASARU , TANIMOTO TAKUMA , ODA HIROTO , TATEYAMA KOICHI
IPC分类号： H01L21/768 , H01L21/822 , H01L23/522 , H01L27/04
摘要： PURPOSE: To provide a small-sized inductor element of low loss which is used in a monolithic microwave IC. CONSTITUTION: A semi-insulating semiconductor substrate 10, an interlayer insulating film 11, a first wiring metal layer 12, and a second wiring metal layer 13 are arranged. The second wiring metal layer 13 is formed to be distant from the semi-insulating semiconductor substrate 10 by using a thick resin insulating film 17 having low dielectric constant. Thereby an inductor element of low loss whose element inductance is constant in a wide band can be formed. In a monolithic microwave IC using the inductor element, high gain, low consumption power and wide band operation are realized.

9. 发明专利

JPH02199843A COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02199843A
公开(公告)日：1990-08-08
申请号：JP1765589
申请日：1989-01-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ODA HIROTO , TAKATANI SHINICHIRO , MIYAZAKI MASARU , SHIGETA JUNJI
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To form sidewalls of a silicon nitride film with good reproducibility by a method wherein the silicon nitride film is etched by making use of sidewalls of a silicon oxide film as a mask. CONSTITUTION:An n-type active channel region 21 is formed on a GaAs substrate crystal 1; a gate electrode 3 and a silicon nitride film 5 are formed on them; a photoresist 71 as a mask material having opening parts in parts corresponding to active channels is formed. Then, Si ions are implanted by making use of the gate electrode 3 as a mask. Then, the photoresist 71 is removed; after that, a silicon oxide film 61 is formed on the silicon nitride film 5; the silicon oxide film 61 is etched selectively and removed by making use of the photoresist 72 as a mask; sidewalls 8 of the silicon oxide film are left on side faces of the gate electrode 3. Then, the exposed silicon nitride film 5 is etched selectively and removed by making use of the sidewalls 8 of the silicon oxide film as a mask; the n ion implantation layer 4 is exposed.

10. 发明专利

JPS63293950A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63293950A
公开(公告)日：1988-11-30
申请号：JP12829587
申请日：1987-05-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISOBE YOSHIHIKO , MIYAZAKI MASARU
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To form an air bridge wiring without restrictions of the forming method of a wiring layer and the kinds of wiring metal, by using silicon resin for an interlayer film which is eliminated in the later process to form the air bridged wiring. CONSTITUTION:After a first wiring layer 1 is processed, a plasma nitride film 2 being a protective film is deposited. If only the protective film has a sufficient selective ratio of etching, one other than the plasma nitride film can be used. A silicon resin 3 is spin-coated and flatten, in which a contact hole 10 is made by dry etching. After a second wiring layer 4 is formed, the silicon resin is eliminated by etching applying hydrofluoric acid, and an air gap 20 is formed. The silicon resin is etched by hydrofluoric acid at a high etching rate, the plasma nitride film is not etched. Thereby, the temperature limitation at the time of forming the wiring metal can be abolished, so that the restriction concerning the wiring metal and its forming method is removed.

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