专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH06209019A HETERO JUNCTION FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPH06209019A
公开(公告)日：1994-07-26
申请号：JP309793
申请日：1993-01-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , SHIGETA JUNJI
IPC分类号： H01L29/812 , C04B41/48 , H01L21/337 , H01L21/338 , H01L29/778 , H01L29/808
摘要： PURPOSE:To realize a high speed and low noise by providing an undoped semiconductor layer wherein energy level of a conductive band is lower than energy level of a channel layer between a channel layer and a barrier layer at a specified thickness. CONSTITUTION:An i-InAlAs buffer layer 7 and a p-InGaAs buffer layer 6 are formed on an InP substrate, and an n-InGaAs channel layer 1, an i-InAs carrier storage layer 2, an i-InAlAs barrier layer 3 and an i-InGaAs cap layer 4 are formed thereon at thicknesses of 15, 1, 10, and 5nm, respectively. After a gate electrode 9 is formed and a surface thereof is coated with an SiO2 film 8, the SiO2 film 8 is removed only in an ohmic layer formation region. The channel layer 1 in the ohmic layer formation region is etched using the SiO2 film 8 as a mask. An ohmic layer 5 is formed by selectively forming the n-InGaAs layer 5 using the SiO2 film 8 as a mask, and an ohmic electrode (Ti/Au) 10 is formed thereon.

2. 发明专利

JPH02199843A COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02199843A
公开(公告)日：1990-08-08
申请号：JP1765589
申请日：1989-01-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ODA HIROTO , TAKATANI SHINICHIRO , MIYAZAKI MASARU , SHIGETA JUNJI
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To form sidewalls of a silicon nitride film with good reproducibility by a method wherein the silicon nitride film is etched by making use of sidewalls of a silicon oxide film as a mask. CONSTITUTION:An n-type active channel region 21 is formed on a GaAs substrate crystal 1; a gate electrode 3 and a silicon nitride film 5 are formed on them; a photoresist 71 as a mask material having opening parts in parts corresponding to active channels is formed. Then, Si ions are implanted by making use of the gate electrode 3 as a mask. Then, the photoresist 71 is removed; after that, a silicon oxide film 61 is formed on the silicon nitride film 5; the silicon oxide film 61 is etched selectively and removed by making use of the photoresist 72 as a mask; sidewalls 8 of the silicon oxide film are left on side faces of the gate electrode 3. Then, the exposed silicon nitride film 5 is etched selectively and removed by making use of the sidewalls 8 of the silicon oxide film as a mask; the n ion implantation layer 4 is exposed.

3. 发明专利

JPH02130838A FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH02130838A
公开(公告)日：1990-05-18
申请号：JP28368488
申请日：1988-11-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAYAMA SATOSHI , KAWADA YUKIHIRO , SHIGETA JUNJI , KODERA NOBUO
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To reduce parasitic capacities between a gate and source, drain electrodes by shortening the ohmic electrodes of source or drain electrode shorter than the length of the gate. CONSTITUTION:An ohmic electrode 3 and an N type layer 4 under the electrode 3 at a source side are rectangular, and its one side has substantially the same length as that of a gate 5, while the length of one side of an ohmic electrode 1 opposed to the gate 5 at a drain side is 1/4 of the length of the gate. Further, an N type layer 2 to the gate 5 is formed in a trapezoidal shape in which its lower side is the same as the length of the gate and its upper side is slightly longer than the ohmic electrode. Further, the ohmic electrode at the drain side is disposed farther from the gate as compared with that at the source side. Since the line of electric force between the drain and the gate electrode metals is generated only in the part of the drain ohmic electrode with this structure, Cgd can be reduced. Further, it has a structure in which the layer 2 is narrowed toward the electrode 1. Thus, the longitudinal direction of the gate is suitably divided, and the drain electrodes are reduced with respect to the gate in the respective zones. This division may be appropriately conducted according to the length (normally gate width Wg) of the gate in the longitudinal direction.

4. 发明专利

JPS6292356A CAPACITIVE DIODE FOR GAAS LSI 失效
公开(公告)号：JPS6292356A
公开(公告)日：1987-04-27
申请号：JP23122685
申请日：1985-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KODERA NOBUO , MATSUNAGA NOBUTOSHI , MIYAZAKI MASARU , KAYAMA SATOSHI , KAMIYANAGI KIICHI , SHIGETA JUNJI , TANAKA HIRONORI
IPC分类号： H01L27/04 , H01L21/338 , H01L21/822 , H01L27/06 , H01L29/812 , H01L29/93
摘要： PURPOSE:To increase the operating upper-limit voltage (withstanding voltage) of a capacitive diode used in a GaAs LSI largely by dividing a high-concentration N channel into two sections and arranging a low-concentration N channel into a configuration that the hihg-concentration N channel is connected to a section where the end surface of a gate electrode is positioned by the low-concentration N channel. CONSTITUTION:When a high-concentration N channel is brought into contact closely with a section just under a gate electrode 1 and biassed so that negative potential is applied to a terminal, currents concentrate to the end surface of the gate electrode 1. A remarkably high electric field caused by a Schottky barrier appears on the end surface of the electrode where currents concentrate. Consequently, the high- concentration N channel is divided into two section i.e. 21 and 22, and a low- concentration N channel 3 is disposed to a section where the end surface of the gate electrode 1 is positioned to a shape that the two sections 21, 22 are connected with each other. An ohmic electrode metal is connected to the low-concentration N channel 3, the ohmic electrode metal is held as one terminal at positive potential, and an end-section boundary line on the ohmic electrode side of a gate metal is positioned onto the surface of an N channel region.

5. 发明专利

JPH07142587A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH07142587A
公开(公告)日：1995-06-02
申请号：JP28305393
申请日：1993-11-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , SHIGETA JUNJI
IPC分类号： H01L27/088 , H01L21/8234
摘要： PURPOSE:To decrease the number of electrodes required for constituting a circuit and to reduce the area of the circuit by forming closed-ring shaped semiconductor layers by etching, and sharing the ohmic electrode for the inverter part of an inverter circuit having an output buffer circuit and an output buffer part. CONSTITUTION:The semiconductor layers of F1, F3, F4 and F5 are linked, and one closed ring is formed, and the semiconductor layers of F2, F3, F4 and F5 are also linked, and one closed ring is formed. Therefore, the FETs from F1 to F5 can be provided in one semiconductor layer. Gate electrodes 6 of F3 and F5 can be constituted of one metal line crossing each closed ring. The drain electrodes of F1 and F2 are connected to the gate electrode 6 with the metal line. Since the metal line is sufficiently long, the widths of the ohmic electrodes on the drain sides of F1 and F2 can be made larger than the gate widths of F1 and F2. The gate widths of F1 and F2 can be miniaturized.

6. 发明专利

JPH05136347A COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS MANUFACTURE 失效
公开(公告)号：JPH05136347A
公开(公告)日：1993-06-01
申请号：JP29577791
申请日：1991-11-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIGETA JUNJI , TAKAZAWA HIROYUKI , FUCHIGAMI NOBUTAKA , MIYAZAKI MASARU
IPC分类号： H01L27/06 , H01L21/338 , H01L21/8232 , H01L29/812
摘要： PURPOSE:To provide a compound semiconductor integrated circuit wherein a gate resistance is reduced and the interference between elements is reduced and to provide its manufacturing method. CONSTITUTION:In a compound semiconductor integrated circuit, a gate-electrode lower-layer part 3 composed of a heat-resistant metal is formed substantially on an active region 2, a gate-electrode upper-layer part 4 composed of a low- resistance metal is formed in such a way that the gate-electrode lower-layer part 3 is covered, and the gate-electrode upper-layer part 4 is connected to an interconnection metal on an insulating film 5 formed at the outside of the active region. The integrated circuit is manufactured by a method wherein, after a pattern for the gate-electrode lower-layer part 3 has been formed, the insulating film 5 is formed, the top part of the gate-electrode lower-layer part 3 is exposed and a pattern for the gate-electrode upperlayer part 4 is formed.

7. 发明专利

JPH04145629A FIELD EFFECT TRANSISTOR AND ITS MANUFACTURE 失效
公开(公告)号：JPH04145629A
公开(公告)日：1992-05-19
申请号：JP26836190
申请日：1990-10-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUMOTO HIDETOSHI , UMEMOTO YASUNARI , SHIGETA JUNJI , KAGAYA OSAMU , MIYAZAKI MASARU , OISHI YOSHIHISA , ODA HIROTO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/417
摘要： PURPOSE:To acquire a FET of low parasitic resistance whose processing margin is ensured by forming a source/drain region of an n -layer whose side surface is inclined in a forward mesa direction. CONSTITUTION:A semiinsulating GaAs substrate 7 whereon an undoped GaAs layer 6, a pGaAs layer 5, an nGaAs layer 4, an undoped AlGaAs layer 3 and an undoped GaAs layer 2 are laminated is etched through an SiO2 mask 1 for a gate to remove layers 2 to 4 and a part of the layer 5. Then, a crystal direction of a substrate 7 whose active layer surface is (100) surface is selected, a mask of an opening whose current direction of an FET is [011-1] is used to form an active layer of an n GaAs layer 8 by epitaxial growth method having different growth velocities; then, (111) surface is developed in a side surface of the layer 8 and a side surface which is inclined in a mesa direction at a specified angle is formed with good reproducibly. Therefore, if the layer 8 is made a source/drain region, a processing margin (y) and a length of a parasitic resistance region can be decided independently, thereby realizing a FET of high characteristics with enough processing margin and less parasitic resistance.

8. 发明专利

JPS6254966A SCHOTTKY GATE FIELD EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6254966A
公开(公告)日：1987-03-10
申请号：JP19384185
申请日：1985-09-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAMIYANAGI KIICHI , MIYAZAKI MASARU , KOBAYASHI MASAYOSHI , KAYAMA SATOSHI , KODERA NOBUO , SHIGETA JUNJI , YANAGISAWA HIROSHI , HASHIMOTO TETSUKAZU , MASUKI JIYUNJI , ISOBE YOSHIHIKO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/08
摘要： PURPOSE:To obtain a short gate MESFET having high performance by disposing the second source and drain regions having lower carrier density than the first source and drain regions between a gate electrode, and the first source region and the drain region respectively. CONSTITUTION:Source and drain regions are formed double and to be self- aligned with a gate electrode, the second source and drain regions 14, 14' of the gate electrode 3 side have relatively low carrier density and shallow depth, the first source and drain regions 4, 4' of the side separated from the gate electrode have high carrier density to form a high performance MESFET having small short channel effect, and low source resistance. The regions 14, 14' are formed by ion implanting at 15 with the electrode 3 as a mask, and the regions 4, 4' of higher carrier density than the regions 14, 14' are separated from the electrode 3 by ion implanting at 9 with the side wall 16 formed on the side of the electrode 3 as a mask. Thus, a high performance MESFET is obtained.

9. 发明专利

JPH07245338A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07245338A
公开(公告)日：1995-09-19
申请号：JP3330994
申请日：1994-03-03
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKAWA TAKESHI , TAKATANI SHINICHIRO , SHIGETA JUNJI , FUCHIGAMI NOBUTAKA
IPC分类号： H01L21/76 , H01L21/265 , H01L27/095
摘要： PURPOSE:To provide a semiconductor device which has a small amount of impurity and levels produced by uncoupled hands and has a high-quality high- resistance layer and its manufacturing method. CONSTITUTION:A high-resistance layer 11 is formed by radiating atomic hydrogen 10 upon the surface of a compound semiconductor substrate 12 and diffusing the hydrogen into the semiconductor from the surface. When the dose of the atomic hydrogen 10 is controlled, the resistance of the layer 11 can be adjusted to a desired value. Therefore, when the hydrogen 10 is supplied to the surface of the substrate 12, the diffusion of the hydrogen into the semiconductor is accelerated. In addition, since the hydrogen introduced into the semiconductor is coupled with other impurities and uncoupled hands and makes levels caused by these point defects inactive, a high-quality high-resistance layer containing a small amount of levels can be obtained. Therefore, not only the high-frequency characteristics, isolation between elements in integrated circuits, etc., can be improved, but also an equivalent circuit having a prescribed resistance value can easily be obtained by controlling the load resistance in a resistance element.

10. 发明专利

JPH06188274A HETERO JUNCTION FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPH06188274A
公开(公告)日：1994-07-08
申请号：JP33699592
申请日：1992-12-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , SHIGETA JUNJI
IPC分类号： H01L27/095 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PURPOSE:To control a decrease in gate forward allowable voltage and gate breakdown strength and control an increase in noise, by using a semiconductor material of reverse conductive type to an operating layer as a cap layer or a spacer layer in EFET or DFET. CONSTITUTION:An operating layer 1 is growth to a thickness of 15nm on a buffer layer 4 and sequentially an un-AlGaAs barrier layer 2 is growth to 10nm and a p-GaAs layer 3 is grown to 10nm by a MBE method. Then, only the element forming region is left and the other regions are isolated by a wet etching. After this, a gate electrode 6 (WSix) is formed and an SiO2 film is coated and then only the regions forming high concentration conductive layers 5 are removed by a dry etching, After recovering damage of the dry etching by a short-time annealing, sing the SiO2 film as a mask, an n-GaAs is selectively growth by a MOVPE method and the high concentration conductive layers 5 are formed, and ohmic electrodes 7 are installed y a lift-off method.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式