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1. 发明专利

JPH02195722A LOGICAL CIRCUIT 失效
公开(公告)号：JPH02195722A
公开(公告)日：1990-08-02
申请号：JP1390389
申请日：1989-01-25
申请人： HITACHI LTD
发明人： KAWADA ATSUMI , ITOU HIROYUKI , TANAKA HIRONORI
IPC分类号： H03K19/0952
摘要： PURPOSE:To improve load driving ability when an output rises by providing an auxiliary FET and an auxiliary NOR circuit as a load driving load element. CONSTITUTION:Before a time T0, an H level is supplied to an input terminal 112, and an L level is supplied to input terminals 113 and 114. Consequently FETs 106 and 109 are turned on, and load elements 106 and 109 are turned on. After the time T0, when the terminal 112 is switched to the L level, a current 504 of the FET 106 reduces as a time passes. Accordingly the current portion obtained by subtracting the current of the reduced FET 106 from an element 102 is used for driving the load. Further the FET 109 of the auxiliary NOR circuit is turned off as well when the signal 112 starts to shift to the L level, and according to the turned-on of the FET 109, a node 116 becomes approximately the same as a supply voltage 101, an auxiliary FET 103 is turned on, and a current 502 is applied. Consequently a load current 501 applied to an output 105 is obtained by subtracting the current of the FET 106 from both elements 102 and 103. Consequently the load driving current is increased, and the load is driven at high speed.

2. 发明专利

JPS6364366A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6364366A
公开(公告)日：1988-03-22
申请号：JP20786086
申请日：1986-09-05
申请人： HITACHI LTD
发明人： MASUDA NOBORU , YAMASHITA HIROKI , TANAKA HIRONORI
IPC分类号： H01L29/812 , H01L21/265 , H01L21/338 , H01L29/80
摘要： PURPOSE:To prevent the increase of the occupying area of an FET due to the displacement of mask alignment by shrinking an ion implantation region in low concentration to the inside of an ion implantation region in high concentration. CONSTITUTION:An ion implantation region 1 in low concentration is shrunk to the insides of ion implantation regions 2 in high concentration. Consequently, the ion implantation region 1 in low concentration does not protrude to the outsides of the ion implantation regions 2 in high concentration so far as the quantity of the displacement of mask alignment is smaller than that of the region 1 shrunk to the inside. The ion implantation region 1 can be brought into contact with the high-concentration ion implantation regions 2 positively. Accordingly, the occupying area of an FET is not increased, thus laying out a semiconductor integrated circuit only by an originally required area.

3. 发明专利

JPS6345866A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6345866A
公开(公告)日：1988-02-26
申请号：JP18840486
申请日：1986-08-13
申请人： HITACHI LTD
发明人： HATTA YASUSHI , SHIGETA JUNJI , UMEMOTO YASUNARI , TANAKA HIRONORI , KOBASHI TAKAHIRO
IPC分类号： H01L27/06 , H01L21/338 , H01L21/8232 , H01L27/08 , H01L29/80 , H01L29/812
摘要： PURPOSE:To prevent short-channel effects and soft errors by a method wherein a large parasitic capacitor to be generated between MESFET-constituting N - type and P-type regions is kept at a constant potential level. CONSTITUTION:A depression-type MESFET is provided with an N-type region 3 formed, self aligned to a gate electrode 2 built of tungsten silicide. The N-type region 3 constitutes a channel, N -type regions 4 and 5 are formed to be in contact with both sides of the channel, and ohmic electrodes 6 and 7 are connected to the N -type regions 4 and 5 at the substrate surface level. The ohmic electrode 6 corresponds to a source, and the ohmic electrode 7 to a drain. The ohmic electrodes 7 and an electrode 9 are connected to a fixed potential level. The connection is so established that a counter-bias be applied between the N -type region 5 and a P-type region 8. This design results in parasitic capacitors CP1 and CP2 between the N -type region 5 and P-type region 8, which prevents the generation of a parasitic capacitor between the N-type region 3 and N -type region 4.

4. 发明专利

JPS6261372A COUPLING METHOD OF GAAS LSI GATE AND OHMIC ELECTRODES 失效
公开(公告)号：JPS6261372A
公开(公告)日：1987-03-18
申请号：JP19940285
申请日：1985-09-11
申请人： HITACHI LTD
发明人： KODERA NOBUO , YANAGISAWA HIROSHI , MIYAZAKI MASARU , KAJITA SHINJI , TANAKA HIRONORI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L21/768 , H01L23/522 , H01L29/80
摘要： PURPOSE:To reduce the layout area by using a contacting hole common for both gate and ohmic electrodes to simplify the coupling of the ohmic electrode with the gate electrode. CONSTITUTION:A Schottky barrier is formed by superposing a gate electrode 1 and an N-channel 2, and an ohmic electrode contact is formed by superposing an ohmic metal 4 on a high density N type layer 3 connected with the N- channel 2 and alloying them. A contacting hole 5 crossing over both the electrode 1 and the metal 4 is formed in an insulating film such as an SiO2 formed on the metals 1 and 4, and wiring metal 6 is disposed to completely cover the hole 5.

5. 发明专利

JPS628395A SEMICONDUCTOR MEMORY CIRCUIT 失效
公开(公告)号：JPS628395A
公开(公告)日：1987-01-16
申请号：JP14474585
申请日：1985-07-03
申请人： HITACHI LTD
发明人： MASUDA NOBORU , HAYASHI TAKEHISA , TANAKA HIRONORI , MASAKI AKIRA , MITSUSADA KAZUMICHI
IPC分类号： G11C11/41 , G11C11/40
摘要： PURPOSE:To increase the action speed at the time of writing by separating a switch FET for writing and reading and enlarging the switch FET used at the time of writing. CONSTITUTION:For the gate width of respective FET, the maximum electric current value which flows to FET 100 and 101 is larger than the maximum electric current value which flows to FET 122 and 123, and further, the maximum electric current value which flows to FET 120 and 121 is larger than it. At the time of the writing action, one side of data lines 170 and 171 for writing is forcibly kept at the low electric potential, other side of them is forcibly kept at the high electric potential from the external part respectively and at the time of reading, only load elements 130 and 131 are connected to the data lines 170 and 171 for writing. At the circuit, since the switches FET 120 and 121 are larger, the high speed writing action can be expected.

6. 发明专利

JPS61206998A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS61206998A
公开(公告)日：1986-09-13
申请号：JP4655385
申请日：1985-03-11
申请人： HITACHI LTD
发明人： MASUDA NOBORU , TANAKA HIRONORI , HAYASHI TAKEHISA , MASAKI AKIRA , MITSUSADA KAZUMICHI
IPC分类号： G11C11/41 , G11C11/40
摘要： PURPOSE:To make soft errors hard to occur by constituting a pair of FET for memory holding of plural FETs connected in series. CONSTITUTION:Drain electrodes and gate electrodes of two FETs J1, J2 and J3, J4 are cross-connected each other and constitute an FET for memory holding. An end of load elements L1, L2 that supply current to the FET for memory holding is connected to power sources VH1, VH2 of high potential side (power sources of the same potential are normally used for VH1, VH2). The drain electrode of the FET J1 is connected to another end of the load element L1, and the source electrode of the FET J1 is connected to the drain electrode of the FET J2. The source electrode of the FET J2 is connected to the power source VL1 of the low potential side. Further, the gate electrodes of FET J1 and J2 are connected to a node B. The FET J3 and J4 are connected similarly.

7. 发明专利

JPS61171158A GAAS IC DEVICE 失效
公开(公告)号：JPS61171158A
公开(公告)日：1986-08-01
申请号：JP1083385
申请日：1985-01-25
申请人： HITACHI LTD
发明人： YAMASHITA HIROKI , TANAKA HIRONORI , HAYASHI TAKEHISA
IPC分类号： H01L29/812 , H01L21/338 , H01L27/06
摘要： PURPOSE:To contrive to diminish back-gate effect by a method wherein an electrode in contact with the substrate of the same potential as the source potential of a FET or more, an element having an active layer, or a wiring is arranged between the FET constituting the IC and an element having a lower potential than the FET's source potential or a wiring in contact with the substrate. CONSTITUTION:An N-type active layer 118 of coupled capacitance is arranged between an FET N-type active layer 104 and resistors 113, 115, and 114 which act as back gate electrodes. This construction can reduce back-gate effect without adding electrodes of higher potential than the FET's source potential because the potential of said layer 118 is 0(V)-+2(V) and the potential of the FET's source electrode 106 is 0(V).

8. 发明专利

JPS5950558A Static type memory device 失效
标题翻译：静态型存储器件
公开(公告)号：JPS5950558A
公开(公告)日：1984-03-23
申请号：JP15961382
申请日：1982-09-16
申请人： Hitachi Ltd
发明人： HAYASHI TAKEHISA , TANAKA HIRONORI , YAMASHITA HIROKI
IPC分类号： G11C11/412 , G11C11/401 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11
摘要： PURPOSE:To reduce wiring resistance by a method wherein a power source line and a load resistor are arranged in an array of memory cells, and then the maximum value of the length of a data line from a point of the connection of the load resistor to a point of the connection of the memory cell is reduced. CONSTITUTION:Each of load resistors R11, R12-Rm1, Rm2 is connected to each of the data lines di at the center of the memory cell array CA, i.e., the position for nearly equally dividing n-pieces of memory cells Mi,k connected in common to each of the data lines di into subgroup (the medium point of the data lines di). The power source line VDD is also arranged in the direction rectangular to the data lines di at the center of the memory cell array CA and then connected in common to the load resistors R11, R12-Rm1, Rm2. As the result, the influence by the resistance of the data lines di is reduced.
摘要翻译：目的：通过将电源线和负载电阻布置在存储单元的阵列中，然后从负载电阻的连接点到数据线的长度的最大值来减少布线电阻，存储单元的连接点减少。构成：负载电阻R11，R12-Rm1，Rm2中的每一个连接到存储单元阵列CA的中心的每个数据线di，即，将n个存储单元Mi，k几乎等分的位置连接对于每个数据线di进入子组（数据线di的中点）的共同点。电源线VDD也沿与存储单元阵列CA的中心的数据线di成矩形的方向排列，然后共同连接到负载电阻R11，R12-Rm1，Rm2。结果，减少了数据线di的电阻的影响。

9. 发明专利

JPS58223361A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS58223361A
公开(公告)日：1983-12-24
申请号：JP10658082
申请日：1982-06-21
申请人： Hitachi Ltd
发明人： YAMASHITA HIROKI , TANAKA HIRONORI , HAYASHI TAKEHISA
IPC分类号： H01L29/80 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/08 , H01L27/095 , H01L27/118
CPC分类号： H01L27/11803
摘要： PURPOSE:To contrive the improvement of the efficiency of utilizing elements by enhancing the degree of freedom of circuit arrangement by a method wherein a plurality of pieces are arranged in matrix form based on unit of FET of previously decided size, and these basic units are combined only by arbitrary numbers. CONSTITUTION:The FET 419 of unit dimensions previously decided as the basic unit, e.g. of the gate width of 5mum is arranged in matrix form on a chip. In this case, a diode is composed by using a drain 403, a gate 405, a source 406, and a low resistant ion implanted layer 402, and the gate 405 of the FET 419 corresponds to the anode, and the drain 403 to the cathode. While, the diode corresponds to the FET 418. When the gate width of FET serving as the basic unit is set at 5mum as in this case, a piece of FET of the basic unit is sufficient in forming the FET of the gate width of 4mum and 5mum, and two pieces of FETs of the basic unit can be used in parallel in forming the gate width of 10mum, the rest is based thereon.
摘要翻译：目的：通过提高电路布置的自由度来提高使用元件的效率的方法，其中基于先前确定的尺寸的FET的单元以矩阵形式布置多个片，并且将这些基本单元组合只有任意数字。构成：先前将单元尺寸的FET 419确定为基本单元，例如。的栅极宽度为5um，以矩阵形式布置在芯片上。在这种情况下，通过使用漏极403，栅极405，源极406和低电阻离子注入层402来构成二极管，FET 419的栅极405对应于阳极，漏极403到阴极。而二极管对应于FET 418.当在这种情况下用作基本单元的FET的栅极宽度设定为5um时，基本单元的一块FET足以形成栅极宽度为4μm的FET 和5mum，并且可以在形成10mum的栅极宽度上并联使用两片基本单元的FET，其余的基于此。

10. 发明专利

JPS58185088A Semiconductor integrated storage device 失效
标题翻译：半导体集成存储设备
公开(公告)号：JPS58185088A
公开(公告)日：1983-10-28
申请号：JP6533982
申请日：1982-04-21
申请人： Hitachi Ltd
发明人： TANAKA HIRONORI , HAYASHI TAKEHISA
IPC分类号： G11C11/413 , G11C7/14 , H01L27/10
CPC分类号： G11C7/14
摘要： PURPOSE:To offset the noises generated to a data line, by providing a dummy word line to each of memory cell blocks divided at plural places and controlling the potential of the dummy word line with a word line selecting address signal. CONSTITUTION:A cell array is divided into blocks A and B. Internal address signals ax4 and -ax4 are supplied to dummy word drivers DWD0 and DWD1 to be controlled. These signals ax4 and -ax4 have adverse phases to each other in correspondence to an external address signal Ax4. For instance, if a selected word line varies within the same block of A A, one of word lines W0-W15 is set at a high level, with another one set at a low level respectively. In this case, signals Ax4 and -ax4 are set at a low level and a high level respectively with the dummy word lines set at a low level respectively. Thus the noises are offset between the word lines in the block A. As a result, the coupling noises generated at the data line and given through the word line are offset.
摘要翻译：目的：通过向分割在多个位置的每个存储单元块提供一个虚拟字线，并通过字线选择地址信号来控制该虚拟字线的电位，来抵消对数据线产生的噪声。构成：单元阵列分为块A和B.内部地址信号ax4和-ax4提供给虚拟字驱动器DWD0和DWD1进行控制。这些信号ax4和-ax4对应于外部地址信号Ax4而具有不利相位。例如，如果所选择的字线在A A的相同块内变化，则字线W0-W15中的一个被设置为高电平，另一个设置在低电平。在这种情况下，信号Ax4和-ax4分别被设置在低电平和高电平，而虚设字线分别设置在低电平。因此，噪声在块A中的字线之间偏移。结果，在数据线处产生并且通过字线给出的耦合噪声被偏移。

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