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1. 发明专利

JPS61287245A MULTILAYER INTERCONNECTION METHOD 失效
公开(公告)号：JPS61287245A
公开(公告)日：1986-12-17
申请号：JP12820185
申请日：1985-06-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYAZAKI MASARU , ISOBE YOSHIHIKO , MASUKI JIYUNJI , YANAGISAWA HIROSHI
IPC分类号： H01L21/3205
摘要： PURPOSE:To obtain flat multilayer interconnection by forming a photoresist spacer near a wiring pattern, rotatably coating a photoresist, etching back it to uniformly cut a raised portion with good controllability. CONSTITUTION:A PSG 30 is coated approx. 1.5mum thick on a wiring layer 20 of approx. 1mum thick on a GaAs substrate 10. A resist spacer 80 of approx. 7mum thick is formed by photocomposing technique by avoiding on the layer 20, and a projection of an interval l 2mum is formed on the entire surface of a wafer. Then, a photoresist 85 is rotatably coated, and uniformly buried. Then, a photoresist and a PSG are etched at 900 at substantially equal speed with mixture gas of CF4+O2, and projections 35 of the PSG are simultaneously exposed. A light emitting spectrum of SiO2 is altered at the moment. Thereafter, when the PSG is etched back at approx. 800nm only for the prescribed time and the resist is removed, a step B is reduced by approx. 200nm, and a step C is restricted to the value of 200nm. Thereafter, a window 60 is opened to provide he second wiring 70. According to this construction, multilayer interconnections are formed efficiently with good yield.

2. 发明专利

JPS6254966A SCHOTTKY GATE FIELD EFFECT TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6254966A
公开(公告)日：1987-03-10
申请号：JP19384185
申请日：1985-09-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAMIYANAGI KIICHI , MIYAZAKI MASARU , KOBAYASHI MASAYOSHI , KAYAMA SATOSHI , KODERA NOBUO , SHIGETA JUNJI , YANAGISAWA HIROSHI , HASHIMOTO TETSUKAZU , MASUKI JIYUNJI , ISOBE YOSHIHIKO
IPC分类号： H01L29/812 , H01L21/338 , H01L29/08
摘要： PURPOSE:To obtain a short gate MESFET having high performance by disposing the second source and drain regions having lower carrier density than the first source and drain regions between a gate electrode, and the first source region and the drain region respectively. CONSTITUTION:Source and drain regions are formed double and to be self- aligned with a gate electrode, the second source and drain regions 14, 14' of the gate electrode 3 side have relatively low carrier density and shallow depth, the first source and drain regions 4, 4' of the side separated from the gate electrode have high carrier density to form a high performance MESFET having small short channel effect, and low source resistance. The regions 14, 14' are formed by ion implanting at 15 with the electrode 3 as a mask, and the regions 4, 4' of higher carrier density than the regions 14, 14' are separated from the electrode 3 by ion implanting at 9 with the side wall 16 formed on the side of the electrode 3 as a mask. Thus, a high performance MESFET is obtained.

3. 发明专利

JPS6310527A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6310527A
公开(公告)日：1988-01-18
申请号：JP15405786
申请日：1986-07-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISOBE YOSHIHIKO , YANAGISAWA HIROSHI , MIYAZAKI MASARU , MASUKI JIYUNJI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/522
摘要： PURPOSE:To realize a decrease in cost and an increase in reliability to form multi-layer interconnection without performing complicated processing, by forming both the part having inorganic-film property and the part having organic-film property and then utilizing the difference between both the properties to perform this processing. CONSTITUTION:Si-contained organic substance shown in a formula, for example, is dissolved in 2-ethoxyethylacetate to obtain a solution having concentration of about 50 wt%. The first metallic wiring layer 4-b having a definite pattern is formed on the circuit-element side of a wafer 4-a in which circuit elements are formed. The solution of the Si-contained organic substance is sticked on the first metallic wiring layer 4-b by rotational coating method. The layer is then baked in the air to form a layer. Ultraviolet radiation is performed so that the film has inorganic-film property, and thereafter the part 4-c having the inorganic-film property is removed from the surface by using hydrofluoric acid-group etching liquid and then phosphorus glass is sticked there so as to form a layer insulating film 4-e. Successively contact holes 4-f are formed in the layer insulating film 4-e by using a photo resist and by plasma dry-etching method. A metallic film 4-g for the second layer interconnection is then piled there to perform selective etching so that this semiconductor device can be obtained.

4. 发明专利

JPS61183943A ELECTRODE WIRING METHOD 失效
公开(公告)号：JPS61183943A
公开(公告)日：1986-08-16
申请号：JP2343585
申请日：1985-02-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYAZAKI MASARU , MASUKI JIYUNJI , ISOBE YOSHIHIKO , YANAGISAWA HIROSHI
IPC分类号： H01L21/3205 , H01L21/88
摘要： PURPOSE:To improve the coverage failure caused by steps of multilayer wirings and the pattern resolution failure, by a method wherein a spacer insulation film almost level with the wiring electrode is formed almost flat by normal process techniques. CONSTITUTION:The first layer electrode 20 is formed on a semiconductor substrate 1 with a thickness of about 1mum. Next, the whole surface is coated with a spacer insulation film 9 with a thickness of about 1mum. Then, masked with a photo resist pattern 100, the spacer insulation film 9 is processed by anisotropic dry etching into spacer pattern 90, 91 around the electrode 20. Successively, when the ratio of scraping speeds between a projection 91 and a flat surface 90 is set at 10 or more by applying an Ar ion beam to the sample almost in parallel, then only the projection is prominently scraped into a form 92. The whole wafer is fattened by being coated with an interlayer insulation film 30 to a thickness of about 700nm. Afterwards, the second layer electrode is formed after processing a contact hole as conventional.

5. 发明专利

JPH04171732A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04171732A
公开(公告)日：1992-06-18
申请号：JP29712790
申请日：1990-11-05
申请人： HITACHI LTD
发明人： MITANI KATSUHIKO , MASUDA HIROSHI , MOCHIZUKI KAZUHIRO , KUSANO CHUSHIRO , YANAGISAWA HIROSHI
IPC分类号： H01L21/285 , H01L21/28 , H01L21/338 , H01L29/80 , H01L29/812
摘要： PURPOSE:To improve controllability and reliability by forming an electrode of gate length corresponding to the film thickness of a germanium layer. CONSTITUTION:For example, an n type arsenic gallium layer 11, an n-type germanium layer 12, and an n type arsenic gallium layer 13 are piled up one after another on a semiinsulating arsenic gallium substrate 10. Next, after oxygen ions are injected to form a high resistance layer 14 in an element isolation region, mesa etching is performed. Then, an n-type germanium layer 12 exposed from the side wall of a formed recess is selectively coated with W films 15 to form gate electrodes. After the n type arsenic gallium layers 11, 13 are overlaid with source and drain electrodes 16, a passivation film and wirings are provided. This can provide extremely short gate electrodes with excellent controllability and uniformity and prevent strain and cracks of the channel zone because of successive pile-ups of semiconductor layers.

6. 发明专利

JPH03232971A DEVICE FOR VAPOR FORMATION OF THIN FILM 失效
公开(公告)号：JPH03232971A
公开(公告)日：1991-10-16
申请号：JP2854890
申请日：1990-02-09
申请人： HITACHI LTD
发明人： YANAGISAWA HIROSHI , MATSUBARA HIROKAZU
IPC分类号： C23C16/02 , C23C16/34 , C23C16/54 , H01L21/31
摘要： PURPOSE:To allow the continuous formation of thin films by a CVD method without absorbing moisture in insulating films of a coating type by providing a means for heating the samples in a predischarge chamber and a means for supplying ozone to the samples. CONSTITUTION:The insulating films of the coating type are first formed by an ordinary spin coating method on the planar samples 14 formed with semiconductor elements. The planar samples 14 are then imposed on a transporting mechanism 15 existing in the predischarge chamber 15 and while the samples are kept heated to 200 deg.C by lamps 18. The ozone generated by an ozone generator 16 is introduced through a nozzle 17 for uniformizing gaseous flow to the surfaces of the planar samples 14. This state is maintained for 20 minutes to bake the insulating films of the coating type. The supply of the ozone is then stopped, and after the inside of the predischarge chamber 11 is evacuated to a vacuum, the planar samples 14 are transported through a gate valve 13 by the transporting mechanism 15 into a plasma reaction chamber 12 where the thin films of SiNx are formed by the plasma CVD method. The formation of the plasma CVD films is possible without exposing the samples to the atm. air after the baking of the insulating films of the coating type.

7. 发明专利

JPS6261372A COUPLING METHOD OF GAAS LSI GATE AND OHMIC ELECTRODES 失效
公开(公告)号：JPS6261372A
公开(公告)日：1987-03-18
申请号：JP19940285
申请日：1985-09-11
申请人： HITACHI LTD
发明人： KODERA NOBUO , YANAGISAWA HIROSHI , MIYAZAKI MASARU , KAJITA SHINJI , TANAKA HIRONORI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L21/768 , H01L23/522 , H01L29/80
摘要： PURPOSE:To reduce the layout area by using a contacting hole common for both gate and ohmic electrodes to simplify the coupling of the ohmic electrode with the gate electrode. CONSTITUTION:A Schottky barrier is formed by superposing a gate electrode 1 and an N-channel 2, and an ohmic electrode contact is formed by superposing an ohmic metal 4 on a high density N type layer 3 connected with the N- channel 2 and alloying them. A contacting hole 5 crossing over both the electrode 1 and the metal 4 is formed in an insulating film such as an SiO2 formed on the metals 1 and 4, and wiring metal 6 is disposed to completely cover the hole 5.

8. 发明专利

JPS61137371A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS61137371A
公开(公告)日：1986-06-25
申请号：JP25970184
申请日：1984-12-07
申请人： Hitachi Ltd
发明人： MORI MUTSUHIRO , YAO TSUTOMU , YANAGISAWA HIROSHI , MIYAZAKI MASARU
IPC分类号： H01L29/80 , H01L29/10
CPC分类号： H01L29/1066
摘要： PURPOSE:To obtain an SIT which has less leakage current between a gate and a source by forming a source region of an overhang structure by etching the upper layer of a substrate laminated with semiconductor layers of different carrier densities, and forming a gate region and a drain region at both sides with the source region as a mask. CONSTITUTION:An N type layer 100 and an N type layer 1d are laminated on an N type semiconductor substrate, not shown, etched to form an overhang structure to the halves of the layers 1d and 100 and a recess 10 at the side of the remaining overhang structure. Then, the side wall of the overhang structure is coated by an insulating film 30, and with the remaining overhang structure as a mask a P type gate region and a P type drain region 1c are formed by ion implanting. Then, an insulating film and an insulating film 31 of fast etching velocity on the regions are coated, and a film 31 is removed while removing a foreign material adhered onto the region. Then, a source electrode 22 is formed on the layer 1d, and a gate electrode 23 is formed on a gate region.
摘要翻译：目的：通过蚀刻层叠有不同载流子密度的半导体层的基板的上层，通过形成突出结构的源极区域来获得栅极和源极之间的漏电流较小的SIT，并形成栅极区域和漏极区域以源区域为掩模。构成：在N +型半导体衬底（未示出）上层压N +型层100和N +型层1d，以对层1d和100的一半进行蚀刻以形成突出结构，并且在其余悬垂结构侧的凹部10。然后，通过绝缘膜30涂覆悬伸结构的侧壁，以剩余的悬垂结构作为掩模，通过离子注入形成P型栅极区域和P型漏极区域1c。然后，涂覆在区域上具有快速蚀刻速度的绝缘膜和绝缘膜31，并且除去附着在该区域上的异物的膜31。然后，在层1d上形成源极22，在栅极区上形成栅电极23。

9. 发明专利

JPS6053457B2 失效
公开(公告)号：JPS6053457B2
公开(公告)日：1985-11-26
申请号：JP13897977
申请日：1977-11-21
申请人： HITACHI LTD
发明人： SHIMOMOTO TAIJI , IMAMURA YOSHINORI , YANAGISAWA HIROSHI , NARAOKA KYOTAKE , KONDO HIROYUKI
IPC分类号： G03F1/00 , G03F1/40 , G03F1/54 , H01L21/027 , H01L21/302

10. 发明专利

JPS6086829A APPLICATOR FOR PHOTO-RESIST 失效
公开(公告)号：JPS6086829A
公开(公告)日：1985-05-16
申请号：JP19425983
申请日：1983-10-19
申请人： HITACHI LTD
发明人： YANAGISAWA HIROSHI , KANEKO TADAO , KOBASHI TAKAHIRO , HASHIMOTO TETSUKAZU , OOHAYASHI HIDEHITO
IPC分类号： B05C11/08 , G03F7/16 , H01L21/027
摘要： PURPOSE:To treat the surface with excellent reproducibility in a short time by heating a sample before applying a photo-resist and exposing the sample in organic compound vapor. CONSTITUTION:A sample wafer is carried to a surface treating mechanism section by a carrying section 19, and loaded on a sample base 14. A reaction-chamber lower section 12 and a heating jig 15 are lifted, and the sample is shifted on the heating jig 15 while the reaction-chamber lower section 12 and a reaction-chamber upper section 13 are fast stuck, thus forming a hermetically sealed reaction chamber. A solenoid valve 111 is opened, and the reaction chamber is evacuated by using a pump 117. The solenoid valve 111 is closed, solenoid valves 112, 113 are opened, the vapor of an organic compound positioned in a bubbler 20 is introduced into the reaction chamber, and the sample is surface-treated. Lastly, the solenoid valve 112 is closed, the solenoid valve 111 is opened, and residual vapor in the reaction chamber is evacuated, thus completing treatment. Accordingly, adhesive properties between the surface of an element and a photo- resist can be improved with excellent reproducibility, and the time of processes can be shortened.

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