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1. 发明专利

JP2005129749A Semiconductor device provided with macro cell for signal distribution 审中-公开
标题翻译：提供信号分配的宏单元的半导体器件
公开(公告)号：JP2005129749A
公开(公告)日：2005-05-19
申请号：JP2003364145
申请日：2003-10-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KUCHIMACHI KAZUHARU , SAKAKIBARA HIDEKI , SAWARA RYUSUKE , SAKAGAMI TOMONARI , MIYAMOTO KAZUHISA
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To solve the problem that power is uselessly consumed in a dummy cell and a driving circuit since conventionally the dummy cell is connected at a part where the using number of signals is small and an equal load structure is attained, in order to suppress a signal arrival time difference between distributed signals in the case of distributing the signals by using a macro cell.
SOLUTION: In order to match with the signal propagation time of the macro cell in which the number of output terminals is the maximum number, the driving circuit and a load adjusting circuit are constituted and the plurality of macro cells in which the number of the output terminals is different are prepared. Since the macro cell in which the number of the output terminals is not the maximum number can be constituted of fewer driving circuits than that of the macro cells in which the number of the output terminals is the maximum number, power consumption is reduced. Also, since there is no need of using the dummy cell used in a conventional technique, the power consumption of the entire semiconductor device is reduced. Even after the connection of wiring is completed by the macro cell in which the number of the output terminals is different, it can be switched to the macro cell in which the number of the output terminals is smaller.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题为了解决在虚拟单元和驱动电路中无用电的问题，由于传统上虚拟单元在信号的使用数量小并且达到等负载结构的部分被连接以便在通过使用宏小区来分配信号的情况下抑制分散信号之间的信号到达时间差。解决方案：为了与输出端子数量为最大数量的宏单元的信号传播时间相匹配，构成驱动电路和负载调整电路，并且多个宏单元的数量的输出端子是不同的准备。由于输出端子数不是最大数量的宏单元可以由比输出端子数为最大数量的宏单元小的驱动电路构成，所以功耗降低。此外，由于不需要使用常规技术中使用的虚设电池，所以半导体器件整体的功耗降低。即使在输出端子数不同的宏单元完成了布线连接之后，也可以将其切换到输出端子数较小的宏单元。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004198269A Semiconductor integrated circuit device 审中-公开
公开(公告)号：JP2004198269A
公开(公告)日：2004-07-15
申请号：JP2002367462
申请日：2002-12-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAWARA RYUSUKE , KURITA KOZABURO , SUZUKI YUJI , KUSUNOKI MITSUGI , SAKAKIBARA HIDEKI
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185 , G06F9/45 , G11C29/00 , G11C29/56
CPC分类号： G01R31/318577
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device equipped with a pulse generation circuit for generating a pulse having a pulse width smaller than a rise time ut to the full amplitude of a transmission signal. SOLUTION: A first signal and a second signal supplied from the outside through a first signal path and a second signal path are each transmitted to the pulse generation circuit; and when a rise time up to the full amplitude at any one of amplification stages in the first signal path and the second signal path is larger than the pulse width of the pulse to be formed by the pulse generation circuit, the phase difference between the first signal and the second signal is related to the pulse width of the first pulse. COPYRIGHT: (C)2004,JPO&NCIPI

3. 发明专利

JP2002298598A SEMICONDUCTOR DEVICE, AND TEST METHOD FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002298598A
公开(公告)日：2002-10-11
申请号：JP2001099323
申请日：2001-03-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OKUMURA ATSUSHI , HASEGAWA MASATOSHI , KOBAYASHI TORU , NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KITAMURA NOBUAKI , YOKOYAMA YUJI , MIYAOKA SHUICHI , SAWAMOTO HIDEO , NISHIYAMA TAKASHI , KUME SHOJI
IPC分类号： G01R31/28 , G01R31/3183 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To provide test technology of a semiconductor device which can output redundancy relieving information to a high speed SRAM in the outside of a LSI at high speed, and can read out redundancy relieving information stored in the SRAM at low speed with a low speed tester after finish of the test. SOLUTION: A test device of a semiconductor device is constituted of a LSI 1 including a BIST circuit and a circuit to be tested, a tester for testing a circuit to be tested of the LSI 1, a SRAM 3 for holding a test result of the circuit to be tested of the LSI 1, or the like. The device is provided with a pass/fail discrimination signal holding circuit 108 holding a pass/fail discrimination signal inside the BIST circuit 10, and a fail bit map data generating circuit 109 outputting fail bit map information at high speed. The device outputs fail bit map information of a DRAM 204 at high speed to the high speed SRAM 3 of the outside of the LSI 1, and reads out fail bit map information of this SRAM 3 with a low speed tester after finish of a test.

4. 发明专利

JP2011069756A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2011069756A
公开(公告)日：2011-04-07
申请号：JP2009221900
申请日：2009-09-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUNAGA YASUYOSHI , SAKAKIBARA HIDEKI , ITO YUKO , NAKAMURA TOMOJI , HAZEYAMA ATSUSHI , KURITA KOZABURO , TSUTSUMIDA MITSUOKI
IPC分类号： G01R31/316
CPC分类号： G01R31/3016 , G01R19/0084 , G01R19/0092 , G01R21/00
摘要： PROBLEM TO BE SOLVED: To shorten the time required for an analog characteristic test of a variable delay circuit or a digital/analog conversion circuit.
SOLUTION: In the semiconductor integrated circuit, at the time of test operation of the variable delay circuit, a ring oscillator is constituted by the variable delay circuit to cause oscillation (S2), and the normality/abnormality of the variable delay circuit is determined by whether or not the ring oscillator satisfies predetermined monotonic increase conditions (S6) and linearity conditions (S7).
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：缩短可变延迟电路或数字/模拟转换电路的模拟特性测试所需的时间。解决方案：在半导体集成电路中，在可变延迟电路的测试操作时，环形振荡器由可变延迟电路构成以产生振荡（S2），并且可变延迟电路的正常/异常由环形振荡器是否满足预定的单调增加条件（S6）和线性条件（S7）来确定。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2002042500A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002042500A
公开(公告)日：2002-02-08
申请号：JP2000218168
申请日：2000-07-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： AKASAKI HIROSHI , SAKAKIBARA HIDEKI
IPC分类号： G11C11/401 , G11C29/00 , G11C29/02
摘要： PROBLEM TO BE SOLVED: To provide a technology for enabling the intrinsic test of memory- macro without providing an exclusive direct connection path and an exclusive pad for test. SOLUTION: This circuit includes a flip-flop section (51) which can fetch an input signal synchronizing with the prescribed clock signal, and a selecting section (52) which can transmit the input signal to the flip-flop section to a post stage instead of its output signal, and the flip-flop circuit (11-1) is constituted. Thereby, a signal can be transmitted without going through the flip-flop section and delivery and reception of a signal can be performed directly between memory-macro and the circuit.

6. 发明专利

JP2001337134A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001337134A
公开(公告)日：2001-12-07
申请号：JP2000154821
申请日：2000-05-25
申请人： HITACHI LTD
发明人： SAKAKIBARA HIDEKI , NAKAYAMA MICHIAKI , KOBAYASHI TORU
IPC分类号： G01R31/26 , G01R31/28 , G11C29/00 , G11C29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, having a simple structure allowing an effective acceleration test. SOLUTION: This integrated circuit device is provided with burn-in signal terminals and signal terminals for general operation, such that the burn-in signal terminals are separated electrically from the signal terminals for the general operation. Since parasitic capacitance or the like to be added to the signal terminals will not be added to the signal terminals, the operation speed will not be reduced. Accordingly, a burn-in signal can be supplied using a simple connection jig, to effectively execute the acceleration test.

7. 发明专利

JP2001222885A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001222885A
公开(公告)日：2001-08-17
申请号：JP2000032636
申请日：2000-02-03
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KOBAYASHI TORU , MIYAOKA SHUICHI , YOKOYAMA YUJI , SAWAMOTO HIDEO , KUME SHOJI
IPC分类号： G06F12/08 , G11C7/10 , G11C11/401 , G11C11/4093
摘要： PROBLEM TO BE SOLVED: To improve the throughput of external output operation of read data for a memory block capable of performing parallel operation. SOLUTION: This circuit is provided with read buffers RB0-RB3 which can hold the read data read out from plural memory blocks BNK0-BNK7 capable of performing the parallel operation corresponding to a state that the read data can not be outputted from an external interface means to the outside, and selecting means 40, 41 and 42 which select the read data read out from the read buffer and give the read data to an external interface means when the state that the read data can not be outputted is eliminated. Thus, when there is the possibility of conflict of resources in the output operation of the read data, the read data is stored in the read buffer, and when there is no possibility, the read data can be outputted directly to the outside, thereby improving the throughput of output operation of the read data.

8. 发明专利

JP2007080283A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2007080283A
公开(公告)日：2007-03-29
申请号：JP2006293469
申请日：2006-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KOBAYASHI TORU , MIYAOKA SHUICHI , YOKOYAMA YUJI , SAWAMOTO HIDEO , KUME SHOJI
IPC分类号： G06F12/00 , G06F12/08 , G11C11/406
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which easily accepts a write access request regardless of an internal memory operational status. SOLUTION: A semiconductor integrated circuit (1) includes a plurality of memory banks (BNK0-BNK7) formed on a semiconductor chip (1A), a plurality of write buffers (WB0-WB3), an external input circuit (I/F1) and a control circuit (MCNT). Each of the plurality of memory banks includes a data input part and a plurality of memory cells periodically requiring stored data refreshing operations. The control circuit controls a corresponding write buffer so as to selectively hold data supplied to the external input circuit in the corresponding write buffer during a period of time for the refresh operation and the read operation of a corresponding memory bank, and control the corresponding write buffer to supply data to the corresponding memory bank after the completion of the refresh operation and the read operation of the corresponding memory bank. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种容易接受写访问请求的半导体集成电路，而不管内部存储器操作状态如何。解决方案：半导体集成电路（1）包括形成在半导体芯片（1A）上的多个存储体（BNK0-BNK7），多个写入缓冲器（WB0-WB3），外部输入电路（I / F1）和控制电路（MCNT）。多个存储体中的每一个都包括周期性地要求存储的数据刷新操作的数据输入部分和多个存储器单元。控制电路控制相应的写入缓冲器，以便在对应的存储体的刷新操作和读取操作的时间段期间选择性地保持提供给相应写缓冲器中的外部输入电路的数据，并且控制对应的写入缓冲器在完成刷新操作和对应的存储体的读取操作之后向对应的存储体提供数据。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2001091590A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001091590A
公开(公告)日：2001-04-06
申请号：JP26676799
申请日：1999-09-21
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KURITA KOZABURO
IPC分类号： G06F11/22 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a technology for detecting the incorrect delay of a logic block without causing a significant increase of product cost. SOLUTION: A self diagnostic circuit comprises a first circuit 601 generating a clock signal for performing scanning operation through a scan path at a rate lower than the actual working rate of a diagnostic block, and a second circuit 602 generating a clock signal for performing supply of pseudo-random numbers to a logic block and collection of output signals therefrom at a rate substantially equal to the actual working rate of the logic block. Consequently, the incorrect delay of the logic block can be detected without reducing the line resistance by enlarging the line width or providing an amplifier in the scan path.

10. 发明专利

JP2013152249A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2013152249A
公开(公告)日：2013-08-08
申请号：JP2013090880
申请日：2013-04-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUNAGA YASUYOSHI , SAKAKIBARA HIDEKI , ITO YUKO , NAKAMURA TOMOJI , HAZEYAMA ATSUSHI , KURITA KOZABURO , TSUTSUMIDA MITSUOKI
IPC分类号： G01R31/316 , G01R31/28 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To shorten the time required for an analog characteristic test of a variable delay circuit or a digital/analog conversion circuit.SOLUTION: In the semiconductor integrated circuit, at the time of test operation of a variable delay circuit, a ring oscillator is constituted by the variable delay circuit to cause oscillation (S2), and the normality/abnormality of the variable delay circuit is determined by whether or not the ring oscillator satisfies predetermined monotonic increase conditions (S6) and linearity conditions (S7).
摘要翻译：要解决的问题：缩短可变延迟电路或数字/模拟转换电路的模拟特性测试所需的时间。解决方案：在半导体集成电路中，在可变延迟电路的测试操作时，环振荡器由可变延迟电路构成，引起振荡（S2），并且可变延迟电路的正常/异常由环形振荡器是否满足预定的单调增加条件（S6）和线性条件（S7）来确定。

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