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1. 发明专利

JP2001222885A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001222885A
公开(公告)日：2001-08-17
申请号：JP2000032636
申请日：2000-02-03
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KOBAYASHI TORU , MIYAOKA SHUICHI , YOKOYAMA YUJI , SAWAMOTO HIDEO , KUME SHOJI
IPC分类号： G06F12/08 , G11C7/10 , G11C11/401 , G11C11/4093
摘要： PROBLEM TO BE SOLVED: To improve the throughput of external output operation of read data for a memory block capable of performing parallel operation. SOLUTION: This circuit is provided with read buffers RB0-RB3 which can hold the read data read out from plural memory blocks BNK0-BNK7 capable of performing the parallel operation corresponding to a state that the read data can not be outputted from an external interface means to the outside, and selecting means 40, 41 and 42 which select the read data read out from the read buffer and give the read data to an external interface means when the state that the read data can not be outputted is eliminated. Thus, when there is the possibility of conflict of resources in the output operation of the read data, the read data is stored in the read buffer, and when there is no possibility, the read data can be outputted directly to the outside, thereby improving the throughput of output operation of the read data.

2. 发明专利

JPH10284687A SEMICONDUCTOR INTEGRATED CIRCUIT AND CELL LAYOUT METHOD 失效
公开(公告)号：JPH10284687A
公开(公告)日：1998-10-23
申请号：JP8274397
申请日：1997-04-01
申请人： HITACHI LTD
发明人： OKADA HIDEHIRO , NAKAYAMA MICHIAKI
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a technology, which can lay out even a relatively large logic block without dividing the block. SOLUTION: When a first logic block A, a second logic block C which is arranged at the neighborhood of the first logic block, and a plurality of I/O cells 21-3 which can give and take the signals between the first logic block and the second logic block and the outside are aligned, the plurality of I/O cells above described are deviated into a direction intersecting the aligning direction of the above described plurality of I/O cells, in correspondence with the layout area of the above described first block and the above described second block. Thus, the relatively large logic block can be arranged without dividing the block.

3. 发明专利

JP2007288204A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2007288204A
公开(公告)日：2007-11-01
申请号：JP2007122227
申请日：2007-05-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAYAMA MICHIAKI , HAMAMOTO MASATO , MORI KAZUTAKA , ISOMURA SATORU
IPC分类号： H01L21/822 , G01R31/26 , G01R31/28 , H01L21/8238 , H01L21/8244 , H01L27/04 , H01L27/092 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To improve layout efficiency of a semiconductor integrated circuit device since an occupation area of a transistor for a first switch and a transistor for a second switch can be reduced. SOLUTION: An n-type well 2, in which one transistor Tp constituting a CMOS circuit is set is electrically connected with a supply voltage line Vdd through a switching transistor Tps, and a p-type well 3, in which the other transistor Tn constituting the CMOS circuit is set is electrically connected with a supply voltage line Vss through a switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit device is being tested. Meanwhile, the latch-up phenomenon is prevented by turning on the switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the supply voltages Vdd and Vss, respectively. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提高半导体集成电路器件的布局效率，因为可以减少用于第一开关的晶体管和第二开关晶体管的占用面积。解决方案：其中设置了构成CMOS电路的一个晶体管Tp的n型阱2通过开关晶体管Tps和p型阱3与电源电压线Vdd电连接，其中另一个构成CMOS电路的晶体管Tn通过开关晶体管Tns与电源电压线Vss电连接。当半导体集成电路器件为半导体集成电路器件时，通过从外部单元断开开关晶体管Tps和Tns并将适合于测试的电位供给n型阱2和p型阱3，可以控制由漏电流引起的热失控被测试。同时，通过接通开关晶体管Tps和Tns并将n型阱2和p型阱3分别设置为电源电压Vdd和Vss来防止闩锁现象。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2002298598A SEMICONDUCTOR DEVICE, AND TEST METHOD FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002298598A
公开(公告)日：2002-10-11
申请号：JP2001099323
申请日：2001-03-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OKUMURA ATSUSHI , HASEGAWA MASATOSHI , KOBAYASHI TORU , NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KITAMURA NOBUAKI , YOKOYAMA YUJI , MIYAOKA SHUICHI , SAWAMOTO HIDEO , NISHIYAMA TAKASHI , KUME SHOJI
IPC分类号： G01R31/28 , G01R31/3183 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To provide test technology of a semiconductor device which can output redundancy relieving information to a high speed SRAM in the outside of a LSI at high speed, and can read out redundancy relieving information stored in the SRAM at low speed with a low speed tester after finish of the test. SOLUTION: A test device of a semiconductor device is constituted of a LSI 1 including a BIST circuit and a circuit to be tested, a tester for testing a circuit to be tested of the LSI 1, a SRAM 3 for holding a test result of the circuit to be tested of the LSI 1, or the like. The device is provided with a pass/fail discrimination signal holding circuit 108 holding a pass/fail discrimination signal inside the BIST circuit 10, and a fail bit map data generating circuit 109 outputting fail bit map information at high speed. The device outputs fail bit map information of a DRAM 204 at high speed to the high speed SRAM 3 of the outside of the LSI 1, and reads out fail bit map information of this SRAM 3 with a low speed tester after finish of a test.

5. 发明专利

JPH11330374A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11330374A
公开(公告)日：1999-11-30
申请号：JP13308198
申请日：1998-05-15
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： NAKAYAMA MICHIAKI , HASHIMOTO TORU
IPC分类号： G06F1/10 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of implementing both clock skew reduction-based high-speed operation and high integration at the same time, by suppressing crosstalk noises occurring in a system clock wiring while utilizing existing diagnostic clock wirings. SOLUTION: A high-performance microprocessor comprises an input/output section, an input/output control section, a memory, a memory control section, an operation processing section, an instruction control section, a clock generating section, a diagnosis control section and the like. The buffer cell of a second- stage buffer 12 in a clock branch circuit included in the clock generating section and the diagnosis control section outputs four output signals with respect to one input signal. A master diagnostic clock output wiring 25 and a slave diagnostic clock output wiring 26 are laid on both sides of such one system clock output wiring 24. The wirings 25 and 26 are used as diagnostic clock wirings during diagnosis, and are fixed to a power supply potential during actual operation to thereby provide an effect similar to that of shield wirings.

6. 发明专利

JPH03116867A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03116867A
公开(公告)日：1991-05-17
申请号：JP25189489
申请日：1989-09-29
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , MIYAOKA SHUICHI , OGATA TAKASHI , KUSUNOKI MITSUGI , ODAKA MASANORI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118
摘要： PURPOSE:To improve an integrated circuit device of this design in degree of integration by a method wherein a P channel MISFET is provided between the base and the emitter of a bipolar transistor of a changing path which constitutes an output stage circuit, and an N channel MISFET is provided between the base and the emitter of a bipolar transistor of a discharge path. CONSTITUTION:In a semiconductor integrated circuit device 1, where a totem pole type output stage circuit is arranged between an operating potential and a reference potential, a P channel MISFET QP, whose base, emitter, and gate are connected to the source, the drain of a bipolar transistor Tr, and a reference potential respectively, is provided between the base and the emitter of the bipolar transistor Tr which constitutes the charging path of an output stage circuit, and an N channel MISFET Qn, whose base, emitter, and gate are connected to the source, the drain of a bipolar transistor Tr, and an operating potential respectively, is provided between the base and the emitter of the bipolar transistor Tr which constitutes the discharge path of an output stage circuit. By this setup, a P channel MISFET and an N channel MISFET can be made to serve as high resistive elements respectively, so that a semiconductor integrated circuit device can be improved in degree of integration by lessening these high resistive elements in occupied area.

7. 发明专利

JP2000058751A SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2000058751A
公开(公告)日：2000-02-25
申请号：JP22559498
申请日：1998-08-10
申请人： HITACHI LTD
发明人： SAKAMOTO MASATOSHI , NAKAYAMA MICHIAKI
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To stabilize a clock synchronous operation for a faster operation frequency of a semiconductor integrated circuit which is operated in synchronous with the clock signal. SOLUTION: In a direct-under region 23 of a first power-source trunk line 20 and a second power-source trunk line, a power-source capacity 60 and a clock driver 70 connected to both power-source wirings are provided. The clock driver is held between the power-source capacity. Since the clock driver is adjacent to the power-source capacity, even when a lager current flows in the middle of clock synchronous operation, the clock driver acquires the voltage fluctuation prevention effect of the power source wiring due to a charge/ discharge action of the power-source capacity directly near the power-source capacity as its source, resulting in prevention of erroneous operation caused by undesired change in a clock signal waveform at high reliability.

8. 发明专利

JPH09232437A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND COMPUTER SYSTEM USING IT 失效
公开(公告)号：JPH09232437A
公开(公告)日：1997-09-05
申请号：JP3917596
申请日：1996-02-27
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI
IPC分类号： G06F15/78 , G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device in which input/ output circuits can be arranged so as to be scattered at the inside of a chip without sacrificing an integration degree by contriving the layout of a metal interconnection for the supply of power. SOLUTION: A microprocessor uses an MCC (microcarrier-for-LSI-chip) package in which an LSI chip is mounted on a substrate by using a C4 (controlled- collapse-chip-connection) bonding technique. In the microprocessor, a logic block and a memory block as well as an input/output circuit cluster 10 which uses input circuits 11a to 11d and output circuits 12a to 12d are arranged on the LSI chip so as to be scattered in the most favorable and arbitrary positions with reference to performance. In the input/output cluster 10, various power supplies as power supplies exclusively used for independent input/output circuits in every input/output circuit cluster 10 are supplied to metal interconnections 13a to 13d from respective C4 bonding pads 7a to 7d and to metal interconnections 15a to 15d for supply of a power supply via connecting vias 14a to 14d.

9. 发明专利

JPH04130764A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04130764A
公开(公告)日：1992-05-01
申请号：JP25020690
申请日：1990-09-21
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , MIYAOKA SHUICHI , MIYAMOTO KAZUHISA , ODAKA MASANORI , IKEDA TAKAHIDE
IPC分类号： H01L21/822 , G11C11/401 , G11C11/408 , H01L21/76 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10
摘要： PURPOSE:To cut down the leakage current of memory array, etc., by a method wherein the semiconductor substrate of the title semiconductor integrated circuit device shall be an SOI substrate wherein an element substrate is junctioned with a structural substrate through the intermediary of an insulating layer, furthermore, the element substrate is divided into multiple islands by isolation regions. CONSTITUTION:The semiconductor substrate in the title semiconductor integrated circuit device shall be an SOI substrate wherein the P type element substrate PSUB (the second substrate) forming a circuit element is joined to a structural substrate through the intermediary of an insulating substrate comprising e.g. silicon oxide. On the other hand, the element substrate PSUB is divided into multiple islands IL1, IL2 by the isolation regions such as the U-shape isolation trenches U2, 4, etc. In such a constitution, the power supply voltage VEE1 (the first power supply voltage) in relatively high absolute value is fed to the island IL1 as the operational power supply while the other power supply voltage VEE2 (the second power supply voltage) in relatively low absolute value is fed to the island IL2 also as the operational power supply. Through these procedures, the leakage current at the memory array, etc., of Bi.CMOS type RAM can be cut down so as to stabilize the operation thereof.

10. 发明专利

JPH02278765A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02278765A
公开(公告)日：1990-11-15
申请号：JP9976089
申请日：1989-04-19
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , MIYAOKA SHUICHI , ODAKA MASANORI
IPC分类号： H01L27/118 , H01L21/82 , H03K19/173
摘要： PURPOSE:To promote a high integration of a bipolar CMOS gate array by installing macrocell in which four adjacent basic cells of an internal logic circuit are arranged in such a way that they are symmetric like a mirror image with respect to an X-direction and a Y-direction. CONSTITUTION:Many basic cells which have been arranged inside an internal logic circuit are arranged in such a way that four mutually adjacent basic cells 8a, 8b, 8c, 8d are symmetric like a mirror image with respect to an X- direction and a Y-direction. Thereby, a macrocell 5 is constituted. When a desired circuit is formed in a macrocell unit in this manner, the number of input/output terminals are reduced as compared with a case where a circuit is formed by combining many basic cells. Accordingly, even when a complicated and large-scale circuit is formed, it is possible to secure a sufficient channel capacity.

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