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1. 发明专利

JP2002299561A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS FABRICATING METHOD 失效
公开(公告)号：JP2002299561A
公开(公告)日：2002-10-11
申请号：JP2001099324
申请日：2001-03-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TSUBAKI TAKASHI , KITAMURA NOBUAKI , NAKAYAMA MICHIAKI , MIYAOKA SHUICHI
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/02 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To confirm correct writing of additional information for enhancing traceability easily and surely in a short time even if the volume of the additional information is increased. SOLUTION: The semiconductor integrated circuit device comprises parity check logic circuits 10a-10d, and fuse circuits 20-27 for writing additional information. The fuse circuits 20-27 are provided at a redundancy fuse repairing section 12 and written, as additional information, with a format code, the start year of wiring, a month code of wiring lot, the wiring lot number, the wiring lot number suffix, the wafer number, the chip address, and the trimming information. A parity bit is written in the least significant bit of the additional information and, at the time of shipment, the parity check logic circuits 10a-10d perform parity check of the additional information and only a semiconductor integrated circuit device 1 written with correct additional information is shipped.

2. 发明专利

JP2000021988A METHOD AND APPARATUS FOR DESIGNING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000021988A
公开(公告)日：2000-01-21
申请号：JP18843898
申请日：1998-07-03
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TAKIGAWA TOSHIICHI , KITAMURA NOBUAKI
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a technology for designing semiconductor device by which the occurrence of readjusting man-hour can be suppressed through estimating and verifying the quantities of logical and wiring resources at an early stage. SOLUTION: A device for designing a semiconductor device applies an embedded array, uses an LSI floor plan CAD system and is constituted of a program processing section, etc., using software based on information on microcell shape species, ordinary cell shape species, and chip shape species, etc. The device selects a chip shape by reading the microcell shape, ordinary cell, and chip cell species based on steps 201-211 at designing of the system and outline and, after designating the arrangement of microcells, estimates the quantity of logical resources. Successively, the device makes the estimation of power supply wiring and ordinary wiring for verifying the laying space of chip wiring and the estimation of wiring among microcells for verifying the laying space of the wiring among microcells as the estimation of the quantity of wiring resources. After designing the system and outline, the device conducts the basic design, and at the same time, executes floor planning.

3. 发明专利

JP2002298598A SEMICONDUCTOR DEVICE, AND TEST METHOD FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002298598A
公开(公告)日：2002-10-11
申请号：JP2001099323
申请日：2001-03-30
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OKUMURA ATSUSHI , HASEGAWA MASATOSHI , KOBAYASHI TORU , NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KITAMURA NOBUAKI , YOKOYAMA YUJI , MIYAOKA SHUICHI , SAWAMOTO HIDEO , NISHIYAMA TAKASHI , KUME SHOJI
IPC分类号： G01R31/28 , G01R31/3183 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To provide test technology of a semiconductor device which can output redundancy relieving information to a high speed SRAM in the outside of a LSI at high speed, and can read out redundancy relieving information stored in the SRAM at low speed with a low speed tester after finish of the test. SOLUTION: A test device of a semiconductor device is constituted of a LSI 1 including a BIST circuit and a circuit to be tested, a tester for testing a circuit to be tested of the LSI 1, a SRAM 3 for holding a test result of the circuit to be tested of the LSI 1, or the like. The device is provided with a pass/fail discrimination signal holding circuit 108 holding a pass/fail discrimination signal inside the BIST circuit 10, and a fail bit map data generating circuit 109 outputting fail bit map information at high speed. The device outputs fail bit map information of a DRAM 204 at high speed to the high speed SRAM 3 of the outside of the LSI 1, and reads out fail bit map information of this SRAM 3 with a low speed tester after finish of a test.

4. 发明专利

JPH0595275A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0595275A
公开(公告)日：1993-04-16
申请号：JP28218691
申请日：1991-10-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MORI KAZUTAKA , KITAMURA NOBUAKI
IPC分类号： H01L21/82 , H03K19/003 , H03K19/0185
摘要： PURPOSE:To allow a 3.3V operation LSI to interface a 5V operation LSI. CONSTITUTION:A MOSFET 113 is interposed between a MOSFET 112 to obtain a high level output and a MOSFET 114 to obtain a low level output. Moreover, the gate is fixed to a 3.3V or power is supplied to the MOSFET 112 via a diode, then a voltage applied to the MOSFETs is set to 3.3V or below to allow the MOSFETs to interface a 5V operation LSI.

5. 发明专利

JPS59229958A MULTIFRAME SYNCHRONOUS TEST SYSTEM 失效
公开(公告)号：JPS59229958A
公开(公告)日：1984-12-24
申请号：JP10413183
申请日：1983-06-13
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： MORI MAKOTO , IWASE YASUMASA , SHIRAISHI YOSHIKATSU , SHIRASAWA SUSUMU , KITAMURA NOBUAKI
IPC分类号： H04J3/14 , H04M3/24 , H04M3/26 , H04Q11/04
摘要： PURPOSE:To classify and assign a trouble occurring to a time-division exchange, to eliminate the need for a communication between controllers, and to simplify a test by facilitating an autonomous test of multiframe synchronism in a digital signal device. CONSTITUTION:When a selection signal (a) is applied to a selection part 106 while a signal (d) is sent out of an interoffice monitor signal sending circuit 100 to a time-division channel 102, a transmit signal (d) is selected and the contents T of a test time slot are inputted to a shift register 107. The signal contents T circulate by eight bits at every time, so they are sent out to all time slots on a connection bus 110. A receiving circuit 101 selects a signal (f) sent from the channel 102 and a signal (e) sent from a gate 108 through a selector 109. Consequently, the signal contents T are inputted by the receiving circuit 101 at the position of the test time slot. Therefore, the test is taken in normal service without exerting any influence upon other time slots.

6. 发明专利

JPH0964279A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0964279A
公开(公告)日：1997-03-07
申请号：JP21847695
申请日：1995-08-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIOZAWA KENJI , KITAMURA NOBUAKI
IPC分类号： H01L21/285 , H01L21/28 , H01L21/822 , H01L27/04 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a technique which can raise the operation speed of a semiconductor integrated circuit which has a MISFET and a resistor element, and also improve degree of integration. SOLUTION: In a semiconductor integrated circuit device which has a MISFETQn1 and a resistor element R, the source region and the drain region of the MISFETQn1 are constituted of the first semiconductor region 7 made on the main surface of the semiconductor substrate 1 and the silicide layer 12 made on the main surface, and the resistor element R is constituted of the second semiconductor region 8 made on the main surface of the semiconductor substrate 1.

7. 发明专利

JPS63240130A SYNCHRONOUS TYPE COUNTER 失效
公开(公告)号：JPS63240130A
公开(公告)日：1988-10-05
申请号：JP7150387
申请日：1987-03-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UEDA MASARU , KITAMURA NOBUAKI
IPC分类号： H03K23/40 , H03K23/00 , H03K23/50 , H03L7/06
摘要： PURPOSE:To simplify the constitution and to quicken the count operation by providing a count-up control gate means controlling the count-up value into 0, +1, +2 based on a two bits control signal. CONSTITUTION:The phase control counter 1 applies the phase control of a count output with three kinds of count up values of 0, +1, +2 depending on supplied two bits phase control signals B1, B2. With the phase control signals of B1=0, B2=0 for example, the most significant bit count signal MSB and the carry signal CRY are kept to the initial state and the count-up value is made substantially zero. With the relation of B1=1 and B2=0, the count-up value is to be +1 and the normal operation is executed. Moreover, in case of B1=0, B2=1, the count-up value is to be +2. Thus, the maximum gate stage number is 4 to attain high speed count and the constitution is made simple by reducing the number of transistors being components of the phase control counter.

8. 发明专利

JPS63107255A NOISE SUPPRESSING CIRCUIT 失效
公开(公告)号：JPS63107255A
公开(公告)日：1988-05-12
申请号：JP25172486
申请日：1986-10-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UEDA MASARU , KITAMURA NOBUAKI
IPC分类号： H03K5/1252 , H03K5/00 , H04L1/00 , H04L25/08
摘要： PURPOSE:To improve the noise discriminating characteristic by providing two shift registers, which transmit a reception digital signal synchronously with the leading edge and the trailing edge of a sampling clock signal, and a majority decision logic circuit which receives output signals consisting of a prescribed number of bits. CONSTITUTION:A noise suppressing circuit consists of two shift registers (flip flops FA1 and FA2 and flip flops FB1 and FB2) which shift a reception digital signal RD synchronously with the leading edge and the trailing edge of a sampling clock signal phis and the majority decision logic circuit which receives output signals having a prescribed number of bits from these shift registers and consists of AND gates AG1-AG6 and NOR gates NOG1 and NOG2. Thus, not only the reception digital signal which is in the high level for a time longer than the period of the sampling clock signal is surely transmitted as reception data but also the reception signal digital signal which is in the high level for a time equal to or shorter than a half period of the sampling clock signal phis is surely eliminated as noise.

9. 发明专利

JPS5812421A DUTY CORRECTING CIRCUIT 失效
公开(公告)号：JPS5812421A
公开(公告)日：1983-01-24
申请号：JP10936181
申请日：1981-07-15
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： HIROSE KAZUTO , IWASE YASUMASA , KAWAGUCHI MASAHARU , TAKEUCHI WATARU , KITAMURA NOBUAKI
IPC分类号： H03K5/04 , F23N5/00 , H03K5/06
摘要： PURPOSE:To easily reproduce an accurate 50% duty waveform, by using a delay circuit, an FF circuit, and a differentiating circuit in combination. CONSTITUTION:An input signal (a) with a period T supplied from an input terminal 1 has been differentiated of rise by a differentiating circuit 7 to obtain a differential output (b). This differential output (b) sets a D type FF circuit 6 directly. The input signal (a) is further supplied to a delay circuit 3, where it is delayed accurately by T/2 to obtain a delay output (c). Then, a rising edge of this delay output (c) resets the FF circuit 6. Therefore, the circuit 6 is set and reset repeatedly, so that the FF circuit 6 outputs a 50% duty rectangular wave, which has the same frequency with the input signal (a) to an output terminal 5. Thus, the accurate 50% duty waveform is reproduced easily.

10. 发明专利

JPS57192062A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57192062A
公开(公告)日：1982-11-26
申请号：JP7646981
申请日：1981-05-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KITAMURA NOBUAKI
IPC分类号： H01L27/082 , H01L21/3205 , H01L21/66 , H01L21/8222 , H01L23/52
摘要： PURPOSE:To perform accurate measurement for checking logical functions of a lower wiring, by providing terminals which are connected to the lower wiring on a wiring channel region via through hole in an interlayer insulating film on the lower wiring in a wiring structure, and using said terminals for checking the logical functions. CONSTITUTION:The wiring channel region 3 is arranged between logic gates 1 and 2 such as an inverter. A first layer Al wiring 4 between blocks forming a multiple layer wiring structure and a second layer wirings 5-9 crossing the wiring 4 are provided longitudinally and laterally in the region 3. The measuring terminals 11 for checking the logic functions are provided in vacant channel parts 10, wherein no upper wiring layer is provided, in the region 3. Namely, the wiring 4 is provided on a phosphorous silicate glass film 13 on a field SiO2 film 12 in the region 3, and the wirings 5-8 are provided thereon through the interlayer insulating film comprising a phosphorous silicate glass film 14. The through holes 15 are formed in the film 14 by utilizing the space for the vacant channel part 10. The Al measuring terminals 11 are deposited in the holes 15 like the second wiring.

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