专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2004198269A Semiconductor integrated circuit device 审中-公开
公开(公告)号：JP2004198269A
公开(公告)日：2004-07-15
申请号：JP2002367462
申请日：2002-12-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAWARA RYUSUKE , KURITA KOZABURO , SUZUKI YUJI , KUSUNOKI MITSUGI , SAKAKIBARA HIDEKI
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/3185 , G06F9/45 , G11C29/00 , G11C29/56
CPC分类号： G01R31/318577
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device equipped with a pulse generation circuit for generating a pulse having a pulse width smaller than a rise time ut to the full amplitude of a transmission signal. SOLUTION: A first signal and a second signal supplied from the outside through a first signal path and a second signal path are each transmitted to the pulse generation circuit; and when a rise time up to the full amplitude at any one of amplification stages in the first signal path and the second signal path is larger than the pulse width of the pulse to be formed by the pulse generation circuit, the phase difference between the first signal and the second signal is related to the pulse width of the first pulse. COPYRIGHT: (C)2004,JPO&NCIPI

2. 发明专利

JPWO2012053063A1 集積回路および試験方法有权
公开(公告)号：JPWO2012053063A1
公开(公告)日：2014-02-24
申请号：JP2012539502
申请日：2010-10-19
申请人：富士通株式会社
发明人：岡本　博 , 博岡本
IPC分类号： G01R31/28
CPC分类号： G01R31/31919 , G01R31/318577 , G01R31/318594 , H03K5/19
摘要： JTAG−LSI10の発振検出回路15は、発振器20の発振信号が入力される入力ピン11とバウンダリレジスタセル12の間に設けられている。発振検出回路15は、発振器20によって出力された信号を入力ピン11から受信し、該信号の周波数をカウントし、周波数がカウンタ上限値以上である場合には、バウンダリレジスタセル12に「1」を記憶させるように制御する。ここで、バウンダリレジスタセル12に記憶された値が「1」である場合には、発振器20とJTAG−LSI10との間の配線経路が適切であると判断できる。

3. 发明专利

JP2010203898A Semiconductor device test circuit, semiconductor device, and method for manufacturing the same 审中-公开
标题翻译：半导体器件测试电路，半导体器件及其制造方法
公开(公告)号：JP2010203898A
公开(公告)日：2010-09-16
申请号：JP2009049285
申请日：2009-03-03
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： ISHIZUKA SATOSHI
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318577
摘要： PROBLEM TO BE SOLVED: To provide a test circuit, a semiconductor device and a method for manufacturing the same, for applying a stress to a node of a combination circuit to which the stress is not applied by only F/F in a burn-in test or a leak test of the semiconductor device, and inhibiting circuit overhead of the semiconductor device.
SOLUTION: The test circuit is combined with the combination circuits 31 and 32 and disposed in the semiconductor device. A transfer gate switch TG is connected between the node N1 and the node N2. A first transistor T1 is connected between the node N2 and a power supply VDD. A second transistor T2 is connected between the node N2 and the ground GND. The transfer gate switch TG, the first transistor T1, and the second transistor T2 operate according to at least one control signal to be supplied from outside the semiconductor device.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种测试电路，半导体器件及其制造方法，用于仅在F / F中施加不施加应力的组合电路的节点的应力老化测试或半导体器件的泄漏测试，并且抑制半导体器件的电路开销。
解决方案：测试电路与组合电路31和32组合并设置在半导体器件中。传输门开关TG连接在节点N1和节点N2之间。第一晶体管T1连接在节点N2和电源VDD之间。第二晶体管T2连接在节点N2和地GND之间。传输门开关TG，第一晶体管T1和第二晶体管T2根据从半导体器件外部提供的至少一个控制信号进行工作。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP4335202B2 Inspection method and design rule verification method of a semiconductor integrated circuit 有权
公开(公告)号：JP4335202B2
公开(公告)日：2009-09-30
申请号：JP2005334437
申请日：2005-11-18
申请人：パナソニック株式会社
发明人：智子延川
IPC分类号： G01R31/28 , H01L21/82
CPC分类号： G01R31/318577

5. 发明专利

JP2007205933A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2007205933A
公开(公告)日：2007-08-16
申请号：JP2006026024
申请日：2006-02-02
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： HIDAKA ITSUO
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318577 , G11C29/48 , G11C2029/3202
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for applying sufficient stress in a memory during a burn-in test without deteriorating the speed of memory access during normal operation.
SOLUTION: The semiconductor integrated circuit comprises a first circuit, a second circuit, and a third circuit. During a scan pass test, an incorporated flip flop comprises a plurality of scan chains operating as a shift register. The second circuit connects input and output signals of the first circuit. The third circuit is connected to the second circuit through the first circuit. The plurality of the scan chains have a first scan chain and a second scan chain. The first scan chain includes the flip flop connecting the input and output signals to the second circuit. The second scan chain does not include the flip flop connecting the input and output signals to the second circuit. When the third circuit receives the second circuit and signal through the flip flop belonging to the first scan chain, the second scan chain of the first circuit operates as the shift register.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路，用于在老化测试期间在存储器中施加足够的应力，而不会降低正常操作期间的存储器访问速度。解决方案：半导体集成电路包括第一电路，第二电路和第三电路。在扫描通过测试期间，并入的触发器包括作为移位寄存器操作的多个扫描链。第二电路连接第一电路的输入和输出信号。第三电路通过第一电路连接到第二电路。多个扫描链具有第一扫描链和第二扫描链。第一扫描链包括将输入和输出信号连接到第二电路的触发器。第二个扫描链不包括将输入和输出信号连接到第二个电路的触发器。当第三电路通过属于第一扫描链的触发器接收第二电路和信号时，第一电路的第二扫描链作为移位寄存器工作。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2005326203A Actual speed inspection method for semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路实际速度检测方法
公开(公告)号：JP2005326203A
公开(公告)日：2005-11-24
申请号：JP2004143208
申请日：2004-05-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIRAMATSU SUSUMU , OO KINYA , FUKUDA AKIKO
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318577
摘要： PROBLEM TO BE SOLVED: To exhaustively perform an actual speed inspection without reducing the working speed in a general mode.
SOLUTION: In a scanning test of a semiconductor integrated circuit, the circuit is operated at a proper frequency in shifting operation and operated in an actual working time in capturing operation, and in order to effectively realize different duty ratios to circuit groups differed in operation frequency characteristics in the capturing operation, duty ratios of the respective clocks are changed in the shifting operation cycle just before the capturing operation cycle, and the respective clocks are set to the same duty ratio in the capturing operation cycle. At that time, an NT signal control circuit generating NT signal designating switching between shifting operation and capturing operation is provided within the semiconductor integrated circuit, so that the operation by the NT signal can be performed within one clock cycle.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在一般模式下不降低工作速度，彻底地执行实际速度检查。
解决方案：在半导体集成电路的扫描测试中，电路在移位操作中以适当的频率运行，并在实际工作时间内进行捕捉操作，并且为了有效地实现与电路组的不同占空比不同在捕获操作中的操作频率特性中，在捕获操作周期之前的移动操作周期中各个时钟的占空比被改变，并且在捕获操作周期中各个时钟被设置为相同的占空比。此时，在半导体集成电路内设置有产生NT移位信号的NT信号控制电路，该信号指定移位操作和捕捉操作之间的切换，从而可以在一个时钟周期内执行NT信号的操作。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP3701954B2 A semiconductor integrated circuit, the electrostatic breakdown voltage testing method and apparatus 有权
公开(公告)号：JP3701954B2
公开(公告)日：2005-10-05
申请号：JP2003272094
申请日：2003-07-08
申请人：松下電器産業株式会社
发明人：稔伊藤
IPC分类号： G01R31/26 , G01R31/00 , G01R31/28 , G01R31/3185 , H01L21/822 , H01L27/04
CPC分类号： G01R31/002 , G01R31/318577

8. 发明专利

JPWO2007083433A1 半導体装置、及び半導体検査方法审中-公开
公开(公告)号：JPWO2007083433A1
公开(公告)日：2009-06-11
申请号：JP2007554819
申请日：2006-11-14
申请人：パナソニック株式会社
发明人：浩志星加 , 浩志星加 , 川野　威 , 威川野
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： G01R31/3008 , G01R31/3004 , G01R31/318533 , G01R31/318575 , G01R31/318577
摘要：スキャンテストシステムを使用し、フリップフロップ(300)の電源配線(401)と、組合せ回路(307)の電源配線(403)とを分離し、かつ、フリップフロップ(300)の出力を、スキャンチェーンの出力端子(306)と、組合せ回路(307)への出力端子(305)とに分離し、組合せ回路(307)への出力は新たにフリップフロップ(300)にロードホールド端子(304)を追加し、信号値を保持するようにすることにより、静止安定待ちと次のテストベクタのパターニングを同時に行うことができ、IDDQテスト時間の短縮を可能とし、システムLSIのIDDQテストを高速化することができる半導体装置、及び半導体検査方法を提供する。

9. 发明专利

JP2008090989A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008090989A
公开(公告)日：2008-04-17
申请号：JP2006274029
申请日：2006-10-05
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： MATSUBAYASHI KOJI
IPC分类号： G11C29/06 , G01R31/26 , G01R31/28
CPC分类号： G01R31/318577
摘要： PROBLEM TO BE SOLVED: To prevent erroneous operation caused by that the prescribed test mode is not set due to defect of a line in a burn-in test.
SOLUTION: In the semiconductor memory device having a control circuit C2 controlling an output of an on-chip compare signal OCC indicating pass/fail of data read from a memory array based on a scan signal SCAN and provided with a logic part, the prescribed terminal PAD out of a plurality of terminals for power source potentials provided in the semiconductor memory device is used for burn-in test. The logic part has a first control circuit C1 controlling an output of the scan signal SCAN based on a signal (VDD/OPEN) from the prescribed terminal PAD on an input path of the scan signal SCAN.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止由于老化测试中的线路缺陷而导致的规定测试模式未被设置的错误操作。解决方案：在具有控制电路C2的半导体存储器件中，控制电路C2基于扫描信号SCAN控制从存储器阵列读取的数据的通过/失败的片上比较信号OCC的输出并且具有逻辑部分，在半导体存储装置中设置的用于电源电位的多个端子中的规定端子PAD用于老化测试。逻辑部分具有第一控制电路C1，其基于来自扫描信号SCAN的输入路径上的规定端子PAD的信号（VDD / OPEN）控制扫描信号SCAN的输出。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007139603A Method of inspecting semiconductor integrated circuit, and design rule verification method 有权
标题翻译：检查半导体集成电路的方法和设计规则验证方法
公开(公告)号：JP2007139603A
公开(公告)日：2007-06-07
申请号：JP2005334437
申请日：2005-11-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NOBEKAWA TOMOKO
IPC分类号： G01R31/28 , H01L21/82
CPC分类号： G01R31/318577
摘要： PROBLEM TO BE SOLVED: To evaluate not only a DC failure or a degeneration fault but also an AC characteristic failure having increasing tendency such as an SI fault (a crosstalk fault, an IR-DROP fault) or a delay fault following miniaturization recently, as an index for performance evaluation of a semiconductor integrated circuit.
SOLUTION: A pattern capable of detecting a glitch fault or the IR-DROP fault between scan chains 14a is inputted by putting a shift register operation into a possible state by utilizing a scan path circuit provided for detecting the degeneration fault of the semiconductor integrated circuit, and the AC characteristic failure is detected by fluctuation of a supply voltage supplied to the semiconductor integrated circuit or a signal voltage inputted into a scan-in terminal 12, or by fluctuation of the frequency of an inspection pattern.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：不仅要评估直流故障或退化故障，还要评估具有增加趋势的交流特性故障，如SI故障（串扰故障，IR-DROP故障）或小型化之后的延迟故障最近，作为半导体集成电路的性能评估指标。解决方案：通过利用提供用于检测半导体的退化故障的扫描路径电路，通过将移位寄存器操作置于可能状态来输入能够检测扫描链14a之间的毛刺故障或IR-DROP故障的图案集成电路，并且通过提供给半导体集成电路的电源电压的波动或输入到扫入端子12的信号电压或检查图案的频率的波动来检测AC特性故障。版权所有（C）2007，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式