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1. 发明专利

JP2011069756A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2011069756A
公开(公告)日：2011-04-07
申请号：JP2009221900
申请日：2009-09-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUNAGA YASUYOSHI , SAKAKIBARA HIDEKI , ITO YUKO , NAKAMURA TOMOJI , HAZEYAMA ATSUSHI , KURITA KOZABURO , TSUTSUMIDA MITSUOKI
IPC分类号： G01R31/316
CPC分类号： G01R31/3016 , G01R19/0084 , G01R19/0092 , G01R21/00
摘要： PROBLEM TO BE SOLVED: To shorten the time required for an analog characteristic test of a variable delay circuit or a digital/analog conversion circuit.
SOLUTION: In the semiconductor integrated circuit, at the time of test operation of the variable delay circuit, a ring oscillator is constituted by the variable delay circuit to cause oscillation (S2), and the normality/abnormality of the variable delay circuit is determined by whether or not the ring oscillator satisfies predetermined monotonic increase conditions (S6) and linearity conditions (S7).
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：缩短可变延迟电路或数字/模拟转换电路的模拟特性测试所需的时间。解决方案：在半导体集成电路中，在可变延迟电路的测试操作时，环形振荡器由可变延迟电路构成以产生振荡（S2），并且可变延迟电路的正常/异常由环形振荡器是否满足预定的单调增加条件（S6）和线性条件（S7）来确定。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2005116994A Semiconductor integrated circuit and design method of semiconductor device 有权
标题翻译：半导体集成电路和半导体器件的设计方法
公开(公告)号：JP2005116994A
公开(公告)日：2005-04-28
申请号：JP2003419076
申请日：2003-12-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MURATA TOMOO , ITO YUKO , ABE AKIO , YAMASHITA TAKEO , YABUKI SHINOBU , ISOMURA SATORU
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To accurately measure the delay variation quantity due to crosstalk noise. SOLUTION: The semiconductor integrated circuit comprises a ring oscillator RO with an odd number of serially connected stages each composed of a plurality of inverters, a first wiring (aggress side wiring) AGG along a wiring (victim side wiring) VIC on a part of the oscillator RO, a pulse generator circuit PGEN for generating first pulses fed to the first wiring AGG, a first buffer (aggressive gate) AG connected between the first wiring AGG and the pulse generator circuit PGEN, and a second wiring connected between the pulse generator circuit PGEN and the first buffer AG. The distance between the first wiring AGG and the wiring VIC on the part of the oscillator RO is shorter than that between the second wiring and the wiring VIC on the part of the oscillator RO. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：准确测量由串扰噪声引起的延迟变化量。解决方案：半导体集成电路包括具有奇数个串联连接级的环形振荡器RO，每个由多个反相器组成，沿着布线（受害侧布线）VIC的第一布线（边缘侧布线）AGG 振荡器RO的一部分，用于产生馈送到第一布线AGG的第一脉冲的脉冲发生器电路PGEN，连接在第一布线AGG和脉冲发生器电路PGEN之间的第一缓冲器（激进门）AG，以及连接在第一布线AGG之间的第二布线脉冲发生器电路PGEN和第一缓冲器AG。振荡器RO部分的第一布线AGG和布线VIC之间的距离比振荡器RO的第二布线和布线VIC之间的距离短。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2013152249A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2013152249A
公开(公告)日：2013-08-08
申请号：JP2013090880
申请日：2013-04-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUNAGA YASUYOSHI , SAKAKIBARA HIDEKI , ITO YUKO , NAKAMURA TOMOJI , HAZEYAMA ATSUSHI , KURITA KOZABURO , TSUTSUMIDA MITSUOKI
IPC分类号： G01R31/316 , G01R31/28 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To shorten the time required for an analog characteristic test of a variable delay circuit or a digital/analog conversion circuit.SOLUTION: In the semiconductor integrated circuit, at the time of test operation of a variable delay circuit, a ring oscillator is constituted by the variable delay circuit to cause oscillation (S2), and the normality/abnormality of the variable delay circuit is determined by whether or not the ring oscillator satisfies predetermined monotonic increase conditions (S6) and linearity conditions (S7).
摘要翻译：要解决的问题：缩短可变延迟电路或数字/模拟转换电路的模拟特性测试所需的时间。解决方案：在半导体集成电路中，在可变延迟电路的测试操作时，环振荡器由可变延迟电路构成，引起振荡（S2），并且可变延迟电路的正常/异常由环形振荡器是否满足预定的单调增加条件（S6）和线性条件（S7）来确定。

4. 发明专利

JP2011124592A Method of designing semiconductor device 有权
标题翻译：设计半导体器件的方法
公开(公告)号：JP2011124592A
公开(公告)日：2011-06-23
申请号：JP2011008423
申请日：2011-01-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MURATA TOMOO , ITO YUKO , ABE AKIO , YAMASHITA TAKEO , YABUKI SHINOBU , ISOMURA SATORU
IPC分类号： H01L21/82 , G06F17/50 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To accurately measure an amount of variation in delay due to crosstalk noise. SOLUTION: The invention includes a ring oscillator RO in which a plurality of inverters are connected in series in an odd-number of stages, a first wiring (aggressive side wiring) AGG provided along a portion of a wiring (victim side wiring) VIC of the ring oscillator RO, a pulse generator circuit PGEN that generates a first pulse to be supplied to the first wiring AGG, a first buffer (aggressive gate) AG connected between the first wiring AGG and the pulse generator circuit PGEN, and a second wiring connected between the pulse generator circuit PGEN and the first buffer AG. A distance between the first wiring AGG and the portion of the wiring VIC of the ring oscillator RO is shorter than a distance between the second wiring and the portion of the wiring VIC of the ring oscillator RO. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：准确测量由于串扰噪声引起的延迟变化量。解决方案：本发明包括其中多个反相器以奇数级串联连接的环形振荡器RO，沿着布线的一部分设置的第一布线（侵略侧布线）AGG（受害侧布线）VIC，生成要提供给第一布线AGG的第一脉冲的脉冲发生器电路PGEN，连接在第一布线AGG和脉冲发生电路PGEN之间的第一缓冲器（激进栅极）AG，以及连接在脉冲发生器电路PGEN和第一缓冲器AG之间的第二布线。第一布线AGG和环形振荡器RO的布线VIC之间的距离比第二布线和环形振荡器RO的布线VIC的部分之间的距离短。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JPH09298242A LOAD DELAY CALCULATION 失效
公开(公告)号：JPH09298242A
公开(公告)日：1997-11-18
申请号：JP13447096
申请日：1996-05-01
申请人： HITACHI LTD
发明人： HIYAMA TORU , ITO YUKO , SUZUKI KATSUKI
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To speedily compute the circuit load delay at elevated accuracy with taking account of the shield effect, by obtaining the load delay corresponding to the load capacity obtained from the source-gate load capacity-circuit load delay characteristic as its circuit load delay. SOLUTION: Expression α-(α/Lsat).X is obtained; it takes a when the length of the source-gate wiring connected to the output is 0, decreases with the increase of the wiring length and amounts to 0 when the circuit load delay in the source-gate wiring length-circuit load delay characteristic saturates at a saturated wiring length Lsat. The load capacity of the wiring is obtained by multiplying the value integrated from 0 to Lsk (actual source-gate wiring length) by the capacity of the wiring per unit length. The circuit load delay corresponding to the load capacity obtained in this delay characteristic is obtained as a source-gate circuit load delay.

6. 发明专利

JPH06350062A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH06350062A
公开(公告)日：1994-12-22
申请号：JP16645993
申请日：1993-06-11
申请人： HITACHI LTD
发明人： KOBAYASHI TORU , ISOMURA SATORU , SHIMIZU ATSUSHI , ITO YUKO , YAMADA TAKEO , MIYAZAWA KENGO
IPC分类号： H01L27/118 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PURPOSE:To accelerate or compensate an operation margin by a method wherein the reference voltage or operation current for an ECL circuit is made variable by means of the information being set in a register or the information formed on a program element that made possible to be written after the circuit test. CONSTITUTION:For an ECL circuit, a reference voltage VBB is fed to the base of a transistor that is driven for the transistor receiving an input signal, and it is determined whether the input signal is in a high level or in a low level. Moreover, the operation voltage is generated by a constant current transistor provided on the emitter that is common-connected to the operating transistor. Constant voltage VCS is fed to the base of that constant current transistor. By making the reference voltage VBB and constant voltage VCS be variable from outside, it is possible to find the circuit that is close to a margin with a margin acceleration test, and conversely, it is possible to compensate the margin.

7. 发明专利

JP2002280454A METHOD FOR DESIGNING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002280454A
公开(公告)日：2002-09-27
申请号：JP2001080683
申请日：2001-03-21
申请人： HITACHI LTD
发明人： ITO YUKO , ISOMURA SATORU
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor device in which accuracy can be enhanced in the calculation of delay or crosstalk noise while realizing highly accurate delay variation due to crosstalk and highly accurate erroneous operation check due to crosstalk. SOLUTION: According to steps S101-S110 of the method for designing a microprocessor, an ASIC, a high speed high performance LSI, or the like; delay calculation is performed using the total capacity while taking account of the actual load after placement and routing, and placement/routing and correction of routing are repeated until transfer in a target cycle can be carried out. Subsequently, delay calculation is performed using the total capacity while taking account of the actual load and crosstalk, and correction of routing is repeated until transfer in a target cycle can be carried out. Furthermore, crosstalk noise is calculated using the total capacity and the coupling capacity while taking account of the actual load, correction of routing is repeated until erroneous operation is eliminated and the data obtained after placement/routing is used as mask data.

8. 发明专利

JP2001093982A WIRING CAPACITANCE CALCULATING METHOD, CROSSTALK DELAY CALCULATING METHOD AND COMPUTER-READABLE RECORDING MEDIUM WITH DATA STORED THEREIN 失效
公开(公告)号：JP2001093982A
公开(公告)日：2001-04-06
申请号：JP26873499
申请日：1999-09-22
申请人： HITACHI LTD
发明人： ITO YUKO , ISOMURA SATORU
IPC分类号： H01L21/82 , G06F17/50 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a calculating method by which parasitic capacitance total to wiring can be obtained at a high speed with a high precision, and a high speed crosstalk delay calculating method by which an excess margin at predic tion can be cut. SOLUTION: With respect to design of an LSI such as a microprocessor, total capacitance Ctotal per unit length is determined for plural models in different conditions: existence of adjacent wiring (a: no adjacent wiring, B: adjacent wiring existing on one side and C: adjacent wiring existing on both sides) and cross rate of cross wiring (i: 0%, ii: 33%, iii: 37% and iv: 100%) are and made into a library for designing an LSI. The characteristics of the total capacitance per unit length are such that the increase rate of capacitance by the increase in cross rate is high in a region where the cross rate is low but the increase rate of capacitance by the increase in cross rate is low in an area, where the cross rate is high and increase rate of capacitance by the increase in cross rate higher when there is no adjacent wiring than when there is an adjacent wiring.

9. 发明专利

JPH08330523A WIRE LAYOUT METHOD 失效
公开(公告)号：JPH08330523A
公开(公告)日：1996-12-13
申请号：JP15994395
申请日：1995-06-02
申请人： HITACHI LTD
发明人： ITO YUKO , ISOMURA SATORU
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04
摘要： PURPOSE: To suppress the peak value of noise in such a lattice wiring as power supply wiring by selectively switching the pitch of the lattice wiring which is virtually arranged in a lattice according to the noise occurrence situation. CONSTITUTION: The pitch, namely an electrical length L1 , of a lattice wiring corresponding to modules MOD 1 and MOD2 corresponds to the noise occurrence situation of the modules. That is, after obtaining a noise compression rate αwhere the peak value of noise to be propagated reaches a specific value or less, the pitch is calculated as an electrical length L0 where the noise compression rate α is obtained and the pitch of the lattice wiring corresponding to the module MOD3, namely an electrical length L2 , can also be calculated in a similar manner. Therefore, the electrical lengths become optimized values to fully reduce the peak value of noise at each lattice point of the power supply wiring although the peak value of the noise generated from each module is relatively large and hence fully stabilizing the operation of a large-scale integrated circuit device LSI.

10. 发明专利

JPH06169026A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06169026A
公开(公告)日：1994-06-14
申请号：JP31974292
申请日：1992-11-30
申请人： HITACHI LTD
发明人： YAMADA TAKEO , KOBAYASHI TORU , ISOMURA SATORU , SHIMIZU ATSUSHI , ITO YUKO , HAYASHIDA TETSUYA , SATO TOSHIHIKO , TANAKA TAMOTSU
IPC分类号： H01L23/02 , H01L23/04 , H01L23/08 , H01L23/24 , H01L23/50
摘要： PURPOSE:To provide a chip carrier type semiconductor integrated circuit device which enhances connection reliability between a semiconductor chip and a package board. CONSTITUTION:A cap 6 which seals a semiconductor chip 5 is made of metal or synthetic resin and designed to absorb a tensile stress which applies to a soldering bump 4 produced by differential thermal expansion coefficients of the semiconductor chip 5, a package board 2 and the cap 6 by deforming the shape of the cap 6.

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