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1. 发明专利

JP2012129408A Cooling system for data center 有权
标题翻译：数据中心冷却系统
公开(公告)号：JP2012129408A
公开(公告)日：2012-07-05
申请号：JP2010280669
申请日：2010-12-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUDA KAZUYA , UCHIDA MARI , SAWAMOTO HIDEO , IDEI AKIO
IPC分类号： H05K7/20 , F25B1/00 , G06F1/20
摘要： PROBLEM TO BE SOLVED: To provide a space-saving cooling system for a data center that can quickly switch from a compression cycle to a natural circulation cycle.SOLUTION: In the cooling system for a data center that includes a compressor (5), a condenser (3), an expansion valve (6), an evaporator (1) for absorbing heat from an electronic apparatus (51), bypass piping (25) bypassing the compressor and passage changeover means (21, 22, 23) and that can operate the passage changeover means to operatively switch between a compression cycle and a natural circulation cycle, the condenser comprises a plurality of divided condensers (3a, 3b), and at least part (3b) of the plurality of divided condensers includes a straight heat exchanger tube extending vertically. With a predetermined amount of liquefied refrigerant stored in the part divided condenser (3b), the other divided heat exchanger (3a) can be used to provide a compression cycle operation.
摘要翻译：要解决的问题：为数据中心提供节省空间的冷却系统，可以快速从压缩循环切换到自然循环循环。解决方案：在用于数据中心的冷却系统中，包括压缩机（5），冷凝器（3），膨胀阀（6），用于从电子设备（51）吸收热量的蒸发器（1）旁路管路（25）绕过压缩机和通道切换装置（21,22,23），并且可以操作通道切换装置以在压缩循环和自然循环循环之间可操作地切换，所述冷凝器包括多个分开的冷凝器（3a ，3b），并且所述多个分开的冷凝器的至少部分（3b）包括垂直延伸的直的热交换器管。在部分分配的冷凝器（3b）中储存有预定量的液化制冷剂的情况下，可以使用另一个分开的热交换器（3a）进行压缩循环运转。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2007080283A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2007080283A
公开(公告)日：2007-03-29
申请号：JP2006293469
申请日：2006-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KOBAYASHI TORU , MIYAOKA SHUICHI , YOKOYAMA YUJI , SAWAMOTO HIDEO , KUME SHOJI
IPC分类号： G06F12/00 , G06F12/08 , G11C11/406
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which easily accepts a write access request regardless of an internal memory operational status. SOLUTION: A semiconductor integrated circuit (1) includes a plurality of memory banks (BNK0-BNK7) formed on a semiconductor chip (1A), a plurality of write buffers (WB0-WB3), an external input circuit (I/F1) and a control circuit (MCNT). Each of the plurality of memory banks includes a data input part and a plurality of memory cells periodically requiring stored data refreshing operations. The control circuit controls a corresponding write buffer so as to selectively hold data supplied to the external input circuit in the corresponding write buffer during a period of time for the refresh operation and the read operation of a corresponding memory bank, and control the corresponding write buffer to supply data to the corresponding memory bank after the completion of the refresh operation and the read operation of the corresponding memory bank. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种容易接受写访问请求的半导体集成电路，而不管内部存储器操作状态如何。解决方案：半导体集成电路（1）包括形成在半导体芯片（1A）上的多个存储体（BNK0-BNK7），多个写入缓冲器（WB0-WB3），外部输入电路（I / F1）和控制电路（MCNT）。多个存储体中的每一个都包括周期性地要求存储的数据刷新操作的数据输入部分和多个存储器单元。控制电路控制相应的写入缓冲器，以便在对应的存储体的刷新操作和读取操作的时间段期间选择性地保持提供给相应写缓冲器中的外部输入电路的数据，并且控制对应的写入缓冲器在完成刷新操作和对应的存储体的读取操作之后向对应的存储体提供数据。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2559398B2 失效
公开(公告)号：JP2559398B2
公开(公告)日：1996-12-04
申请号：JP6101387
申请日：1987-03-18
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , UMENO HIDENORI
IPC分类号： G06F12/10 , G06F9/46 , G06F12/14

4. 发明专利

JPS6428759A MEMORY PROTECTING SYSTEM 失效
公开(公告)号：JPS6428759A
公开(公告)日：1989-01-31
申请号：JP18331687
申请日：1987-07-24
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO
IPC分类号： G06F12/14
摘要： PURPOSE:To extend the addresses of a virtual space and a real space by dividing the virtual space in two of VA and VB, dividing the real space into two of RA, and RB and protecting a storage to a space pair VA-RA and VB-RB obtained by an address conversion. CONSTITUTION:The virtual space is divided into the two of the virtual space VA of the part of a virtual address 0 to alpha-1 and the partial virtual space VB from a virtual address alpha to M and a boundary address (alpha) is held in a virtual space boundary register VBNND 3. The real space 2 is also divided into the two of the partial real space RA from a real address 0 to beta-1 and the partial real space RB from a real address beta to N and held in a boundary register RBND 4. Then, according to the address conversion, the space VA is mapped on the RA ad and the space VB on the RB, in the space pair VA-RA, the memory is protected in a main storing key 5 disposed for every block of the space RA and in the space pair VB-RB, the memory is protected for every space VB.

5. 发明专利

JPS63231550A MULTIPLE VIRTUAL SPACE CONTROL SYSTEM 失效
公开(公告)号：JPS63231550A
公开(公告)日：1988-09-27
申请号：JP6542487
申请日：1987-03-19
申请人： HITACHI LTD
发明人： SHIMIZU NAOHIKO , SAWAMOTO HIDEO
IPC分类号： G06F12/10
摘要： PURPOSE:To improve a buffer hitting ratio by making effective the actual address of an address converting buffer entry when a virtual address, an address converting table starting point address or an address converting buffer entry, in which a space identifier is coincident or the virtual address and a group identifier are coincident, exists. CONSTITUTION:When the logical address of a memory address register 1 shows the area of a group A, the output of an exclusive OR circuit 6 comes to be '1'. At this time, since an address converting table starting point address ATO of an address converting table starting point register ATOR2 and the ATO of an address converting buffer TLB4 are different, the output of an exclusive OR circuit 5 is '0', and since an area 101 of the group A is not all common areas 100, the C bit of a TLB4 is also '0'. In this case, when a group ID (GID) is not set, namely, circuits 7-9 do not exist, the output of an OR circuit 10 is '0', the output (HIT signal) of an AND circuit 11 comes to be '0', and is decided to be not TLB.

6. 发明专利

JPS61125659A Address converting system for virtual computer system 失效
标题翻译：虚拟计算机系统地址转换系统
公开(公告)号：JPS61125659A
公开(公告)日：1986-06-13
申请号：JP24768284
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： SAWAMOTO HIDEO
IPC分类号： G06F12/10 , G06F12/08
摘要： PURPOSE: To reduce the performance overhead of a VM due to the calculation to the VM by executing directly an LRA instruction with no convention of the VM.
CONSTITUTION: In case an address conversion buffer TLB contains no pair of address converters while a VM needed for 2-level address conversion is running, the branching is led to a 2-level address conversion routine of a microprogram. Then the 2-level address conversion is carried out by the control of the microprogram, and the branching returns from the address conversion. In other words, a segment table ST on a main memory and a page table PT are retrieved without using the TLB in the case of an LRA instruction. Thus a real address is obtained. When the LRA instruction is produced from the VM, the branching is led to a 2-level address conversion LRA routine in the case of a VM which performs the 2-level address conversion.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了通过直接执行没有VM惯例的LRA指令来减少由于对VM的计算而导致的VM的性能开销。构成：如果地址转换缓冲区TLB在运行2级地址转换所需的VM时，不存在一对地址转换器，则分支将导致微程序的2级地址转换程序。然后通过微程序的控制执行2级地址转换，并且从地址转换返回分支。换句话说，在LRA指令的情况下，检索主存储器上的段表ST和页表PT，而不使用TLB。因此，获得了真正的地址。当从VM产生LRA指令时，在执行2级地址转换的VM的情况下，将分支引导到2级地址转换LRA例程。

7. 发明专利

JPS59218693A Address converting system 失效
标题翻译：地址转换系统
公开(公告)号：JPS59218693A
公开(公告)日：1984-12-08
申请号：JP9375483
申请日：1983-05-27
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： TAJIRI KAZUO , INOUE MASANOBU , SAWAMOTO HIDEO , UEDA KOUICHI
IPC分类号： G06F12/10 , G11C9/06 , G06F13/00
CPC分类号： G06F12/10
摘要： PURPOSE:To increase the independent characteristics of a virtual address space for address conversion of an information processor applying a multiplex virtual address system by invalidating the effect of a bit (c) to a specific virtual address space VS and allotting different programs or data to the virtual addresses which are used with the allotment of common programs or data for other plural spaces VS. CONSTITUTION:When VS1 or VS2 is switched to VS3, a control program sets 3 as VSID11 of a register 9, the head address of an address conversion table corresponding to the VS3 as ATO10 and 1 to an I bit 12 since the VS3 has no program nor data 4 common to the VS1 or VS2. As a result, the output of an AND gate 22 is set at 0 regardless of (c) bit 17. Then a TLB entry which has VS15 coincident with VA18 and VSID14 coincident with the VSID11 of the TR9 (3 in this case) can be used for address conversion of the VA18. In other words, only (3,a,delta,c=0) can be used for the conversion of a virtual address (a). Then (1,a,alpha,c=1) or (2,a,alpha,c=1) is never used by mistake even though they remain within a TLB.
摘要翻译：目的：通过使比特（c）对特定虚拟地址空间VS的影响无效并将不同的程序或数据分配给该虚拟地址空间VS来增加用于应用多路复用虚拟地址系统的信息处理器的地址转换的虚拟地址空间的独立特性虚拟地址与其他多个空间VS的公用程序或数据的分配一起使用。构成：当VS1或VS2切换到VS3时，控制程序将3设为寄存器9的VSID11，将VS3作为ATO10和1对应的地址转换表的头地址设置为I位12，因为VS3没有程序也不是对VS1或VS2通用的数据4。结果，与（c）位17相比，AND门22的输出被设置为0.然后，与TR9（在这种情况下为3）的VSID11一致的具有VS15的VS15一致的TLB条目可以是用于VA18的地址转换。换句话说，只有（3，a，delta，c = 0）可以用于虚拟地址（a）的转换。那么即使它们保留在TLB内，也不会错误地使用（1，a，α，c = 1）或（2，a，α，c = 1）。

8. 发明专利

JPS58178448A Data processor 失效
标题翻译：数据处理器
公开(公告)号：JPS58178448A
公开(公告)日：1983-10-19
申请号：JP6105382
申请日：1982-04-14
申请人： Hitachi Ltd
发明人： SAWAMOTO HIDEO
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： PURPOSE:To preserve information on input data accurately without increasing hardware in amount, by adding even parity data to output data on an invalid address. CONSTITUTION:Data on an invalid address (shown by *) consists of data bits 0, 1, and 2 where the address is written as it is, and an even parity bit. If input data changes into 011 erroneously, parity error information such as 0110 is read out of an ROM and set in a DR5, and an error detecting circuit 2 detects the error to freeze an AR3 and the DR5. At this time, the DR5 is stored with 0110, which coincides with data on address 011, so it is evident that the parity error is caused by an input data error and its address is 011.
摘要翻译：目的：为了在不增加硬件量的情况下准确保存输入数据的信息，通过将偶校验数据添加到无效地址的输出数据上。构成：无效地址（由*表示）的数据由地址按原样写入的数据位0,1和2组成，偶数奇偶校验位。如果输入数据错误地变为011，则从ROM中读出诸如0110的奇偶校验错误信息并设置在DR5中，并且错误检测电路2检测到冻结AR3和DR5的错误。此时，DR5与0110一起存储，与地址011上的数据一致，因此显然奇偶校验错误是由输入数据错误引起的，其地址为011。

9. 发明专利

JPS5778692A Memory access system of electronic computer 失效
标题翻译：电子计算机存储器访问系统
公开(公告)号：JPS5778692A
公开(公告)日：1982-05-17
申请号：JP15551180
申请日：1980-11-04
申请人： Hitachi Ltd
发明人： IKEDA KOUICHI , SAWAMOTO HIDEO
IPC分类号： G06F12/10
CPC分类号： G06F12/10
摘要： PURPOSE:To shorten a memory access overhead time, by converting an address to a real memory address from a virtual memory address, until the address from a processing device is inputted after a memory device has received an access request. CONSTITUTION:A logical address is set to a logical address register 12 by an instruction M0 and a signal CLK1, and at the same time, a memory access request FF3 is set, and an access request is transferred 4 to a memory device. Subsequently, the logical address is inputted to an address converting device 6, and as a result, a real address is outputted. This real address is stored in a real address register 7 by an instruction M1 and the clock signal CLK1. The memory device which has received the access request signal 4 outputs an address request signal 8 when this request has been received. In this way, contents of the register 7 are outputted 10 through an AND gate 9, and the address is transferred to the memory device.
摘要翻译：目的：通过将地址转换为虚拟存储器地址的实际存储器地址来缩短存储器访问开销时间，直到在存储器件接收到访问请求之后输入来自处理设备的地址。构成：通过指令M0和信号CLK1将逻辑地址设置到逻辑地址寄存器12，同时设置存储器访问请求FF3，并将访问请求4传送到存储器件。随后，将逻辑地址输入到地址转换装置6，结果输出实地址。该实际地址由指令M1和时钟信号CLK1存储在实地址寄存器7中。已经接收到访问请求信号4的存储装置在接收到该请求时输出地址请求信号8。以这种方式，寄存器7的内容通过与门9输出10，地址被传送到存储器件。

10. 发明专利

JP2510605B2 失效
公开(公告)号：JP2510605B2
公开(公告)日：1996-06-26
申请号：JP18332287
申请日：1987-07-24
申请人： HITACHI LTD
发明人： ARA MARI , SAWAMOTO HIDEO , YAMAGATA MAKOTO
IPC分类号： G06F9/46 , G06F12/10

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