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21. 发明专利

JPS5753145A Calibrator for analogue-digital converter 失效
标题翻译：模拟数字转换器校准器
公开(公告)号：JPS5753145A
公开(公告)日：1982-03-30
申请号：JP12818180
申请日：1980-09-16
申请人： Sony Tektronix Corp
发明人： MUROOKA RIKICHI
IPC分类号： H03M1/10 , G01R13/06 , G01R13/20 , G01R35/00 , H03M1/00 , H03M1/18
CPC分类号： G01R35/005 , G01R13/06 , H03M1/10
摘要： PURPOSE: To eliminate the error in the whole of an analogue-digital converter (ADC), by applying the first, the second, and the third reference levels to an amplifier placed before the converter and by controlling the DC level and the gain of the amplifier in accordance with the digital value.
CONSTITUTION: In case that the DC level is corrected, a switch 19 is switched to the side of a resistor 20, and the input side of an amplifying circuit 8 is caused to fall to the ground level. The output of the amplifying circuit 8 is applied to an ADC12 through a sampling hold circuit 10 and becomes a digital signal. This signal is written in a memory 13 and is compared with the first reference value of a ROM16 in a control circuit 14, and a digital-analogue converter DAC23 is controlled by the comparison result to correct the DC level. Next, positive and negative second and third reference voltages are applied to an attenuator 4 through a switch 3, and the digital value of the ADC12 and the second reference value of the ROM16 are compared with each other, and the DAC24 is controlled by the comparison result to correct the gain.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：为了消除整个模拟数字转换器（ADC）中的误差，通过将第一，第二和第三参考电平应用于放置在转换器之前的放大器，并通过控制直流电平和增益放大器按照数字值。构成：在DC电平校正的情况下，将开关19切换到电阻器20的一侧，使放大电路8的输入侧降至接地电平。放大电路8的输出通过采样保持电路10施加到ADC12，并成为数字信号。将该信号写入存储器13中，并将其与控制电路14中的ROM16的第一参考值进行比较，并通过比较结果控制数模转换器DAC23以校正DC电平。接下来，通过开关3将正和负的第二和第三参考电压施加到衰减器4，并且将ADC12的数字值和ROM16的第二参考值相互比较，并且通过比较来控制DAC24 导致纠正增益。

22. 发明专利

JPS5698012A AMPLITUDE LIMITING CIRCUIT 失效
公开(公告)号：JPS5698012A
公开(公告)日：1981-08-07
申请号：JP51380
申请日：1980-01-09
申请人： SONY TEKTRONIX CORP
发明人： ISHIJIMA YASUMORI , MUROOKA RIKICHI
IPC分类号： H03G11/00 , H03G11/02
摘要： PURPOSE:To eliminate an evil effect to be given to the signal source, by cutting off the output terminal from the input terminal in the mode of amplitude limitation. CONSTITUTION:The outputs of both the comparators 26 and 28 are 0 when the input signal voltage Vi has a relation of -V2

23. 发明专利

JP2000231701A INSPECTION DEVICE FOR MAGNETIC DISK MEDIUM 失效
公开(公告)号：JP2000231701A
公开(公告)日：2000-08-22
申请号：JP3201499
申请日：1999-02-09
申请人： SONY TEKTRONIX CORP
发明人： MUROOKA RIKICHI , OHIGATA YASUHIRO
IPC分类号： G11B5/00
摘要： PROBLEM TO BE SOLVED: To suffice the not many number of retrying times at the inspection by reducing the noise generated due to a magnetic disk medium itself. SOLUTION: A high-pass filter 19 is set so that the noise in a read-out signal generated due to the magnetic disk medium 10 itself, particularly the frequency lower than the fundamental frequency of the read-out signal is cut. Further, the frequency higher than the fundamental frequency of the read-out signal is cut as well by the low-pass filter 16.

24. 发明专利

JPH08128965A SURFACE INSPECTION DEVICE 失效
公开(公告)号：JPH08128965A
公开(公告)日：1996-05-21
申请号：JP28875694
申请日：1994-10-28
申请人： SONY TEKTRONIX CORP
发明人： MUROOKA RIKICHI
IPC分类号： G01B11/30 , G01J1/02 , G01N21/88 , G01N21/93 , G01N21/95 , G11B5/84 , G11B7/26
摘要： PURPOSE: To easily inspect the surface and rotating state of a subject by emitting a band light onto the surface of the rotatable subject at a fixed incident angle, successively measuring the illuminance change of the reflected light to determine a standard characteristic as a function of reflecting angle, and providing an optical line sensor out of the maximum illuminance position. CONSTITUTION: A light source 10 emits a light made into band by a slit onto the inspection line on a disc 2 to be inspected at a prescribed incident angle. The image of the reflected light is taken by an optical line sensor 14 consisting of CCD, and the illuminance is successively measured as a function to reflecting angle. From the result, the standard characteristic of illuminance change of the reflected light is determined as the function of reflecting angle and stored. The sensor 14 is situated in a position having a level lower than 1/2 of the maximum illuminance value in the standard characteristic. The reflected light scanned by the band light is then measured during the rotation of the disc 12, and compared with the standard characteristic to inspect the surface state and rotating state of the disc 12. The processing therefor is performed by an image processing device 16 and a computer 18.

25. 发明专利

JPH0135303B2 失效
公开(公告)号：JPH0135303B2
公开(公告)日：1989-07-25
申请号：JP7202684
申请日：1984-04-11
申请人： SONY TEKTRONIX CORP
发明人： TAKEUCHI SUMIO , MUROOKA RIKICHI
IPC分类号： G01R13/20

26. 发明专利

JPS60214266A Signal storage device 失效
标题翻译：信号存储设备
公开(公告)号：JPS60214266A
公开(公告)日：1985-10-26
申请号：JP7202684
申请日：1984-04-11
申请人： Sony Tektronix Corp
发明人： TAKEUCHI SUMIO , MUROOKA RIKICHI
IPC分类号： G01R13/20
摘要： PURPOSE: To store an input signal roughly and also store respective aimed parts finely by storing the input signal in plural sub memory areas almost at the time point of the generation of each trigger signal according to a high-frequency clock signal.
CONSTITUTION: An A/D converter 12 converts the input signal into a digital signal according to the high-frequency clock H; and the 1st memory 32 stores the signal when a low frequency clock L is generated and the 2nd W the 4th memories 34W38 store the signal when the high frequency clock H is generated. When a trigger circuit 14 generates the 1st trigger signal, a memory control circuit 40 stops the writing operation of the 2nd memory 34 a specific time later and then stops the writing operation of the 3rd and the 4th memories 36 and 38 a specific time after the 2nd and the 3rd trigger signals are generated. The memory control circuit 40, on the other hand, counts the low frequency clock L up to a specific number and then stops the writing operation of the 1st memory 32. Then, an MUX42 selects the 1st W the 4th memories during reading operation and a desired waveform is displayed on a CRT46.
COPYRIGHT: (C)1985,JPO&Japio
摘要翻译：目的：通过大致地存储输入信号，并且通过根据高频时钟信号几乎在产生每个触发信号的时间点将输入信号存储在多个子存储区域中，精细地存储各个目标部分。构成：A / D转换器12根据高频时钟H将输入信号转换为数字信号; 并且当产生低频时钟L时，第一存储器32存储信号，并且当产生高频时钟H时第二 - 第四存储器34-38存储信号。当触发电路14产生第一触发信号时，存储器控制电路40停止特定时间的第二存储器34的写入操作，然后在第三和第四存储器36和38的写入操作之后的特定时间停止产生第二和第三触发信号。另一方面，存储器控制电路40将低频时钟L计数到特定数量，然后停止第一存储器32的写入操作。然后，MUX42在读取操作期间选择第1 - 第4个存储器，并且a 期望的波形显示在CRT46上。

27. 发明专利

JPS60177270A SIGNAL STORAGE DEVICE 失效
公开(公告)号：JPS60177270A
公开(公告)日：1985-09-11
申请号：JP3224784
申请日：1984-02-22
申请人： SONY TEKTRONIX CORP
发明人： MUROOKA RIKICHI
IPC分类号： G01R13/20
摘要： PURPOSE:To measure precisely the time between two points accurately by switching write clock signal frequencies with a trigger signal, and measuring the time from the last 1st clock signal to the starting 2nd clock signal. CONSTITUTION:When a comparator 16 generates the trigger signal, the output of a latch circuit 28 goes up to a high level, and an electronic switch 21 supplies a high-frequency clock signal A as a write clock signal to an A/D converter 14 and an address generator 24. A counter 76 on the other hand, is in operation before the generation of the trigger signal to count the high-frequency clock signal A, and is reset every time a pulse of a low-frequency clock signal B is generated. When the trigger signal is generated, a terminal E of the counter 76 falls to a low level and the counter 76 stops counting operation. Then, when the time between two points including the trigger point is measured, the contents of the counter 76 are read by a CPU and the value is considred to calculate the accurate time.

28. 发明专利

JPS59223987A STORAGE DEVICE OF DIGITAL SIGNAL 失效
公开(公告)号：JPS59223987A
公开(公告)日：1984-12-15
申请号：JP9312383
申请日：1983-05-26
申请人： SONY TEKTRONIX CORP
发明人： MUROOKA RIKICHI , KOYAMA TETSUO , TSUKAMOTO TAKUROU , IWASA TETSUO , TAKAHASHI HISAO , KURATA MAKOTO
IPC分类号： G11B20/10 , G06F12/06 , G06F12/08 , G11C7/00 , G11B5/09 , G11C9/06
摘要： PURPOSE:To obtain a high-speed and large-capacity digital signal storage device by using N (N is an integer of >=3) pieces of serial-input serial-output type shift registers as high-speed small-capacity storage elements, and memories, such as RAM, etc., as low-speed large-capacity storage elements. CONSTITUTION:After writing is completed, each shift register 12-1-12-4 successively sends digital signals stored by means of the 2nd clock signal, whose frequency is lower than that of the 1st clock signal, to corresponding memories. Namely, of the N pieces shift registers only one shift register is in the writing operation and the others are in the reading out operation. Since the N is an integer of >=3, only 1/(N-1) of the writing speed is sufficient for the reading out speed of each shift register and the writing speed of the memories can be delayed by the amount. Moreover, since outputs of the shift registers are supplied to the memories 18-1-18-4 without passing through storage elements, such as latch circuit, etc., a low reading out speed obtained by the combination of the shift registers can be applied to the writing speed of the memories under the same condition. Therefore, an efficient high-speed large-capacity digital signal storage device is obtained when compared with conventional techniques.

29. 发明专利

JPS58216962A Logic analyser 失效
标题翻译：逻辑分析仪
公开(公告)号：JPS58216962A
公开(公告)日：1983-12-16
申请号：JP9657083
申请日：1983-05-31
申请人： Sony Tektronix Corp
发明人： YOKOGAWA HIDEMI , MUROOKA RIKICHI , FUKUZAWA MIYUKI , TOMIOKA MACHIKO
IPC分类号： G01R13/28 , G01R13/20 , G06F11/25
CPC分类号： G06F11/25 , G01R13/20
摘要： PURPOSE:To make it possible to discriminate data containing by a method wherein a glitch is detected from an input logic signal by a glitch detecting means and the display of the character of the input signal containing the glitch is controlled by a character display control means. CONSTITUTION:The data component and the glitch component among the input logic signals from a probe 10 are stored by respective memory circuits 14, 18 through a block 12 and, when a display order is inputted from a keyboard 30, CPU24 transmits the memory contents of the memory circuits 14, 18 to RAM28 on the basis of the firm wear of ROM26. In addition, a display mode and display region information selected by the keyboard 30 are stored by RAM 28 and a display control circuit 32 repeatedly read the content of the display RAM region of RAM28 to display a logic state by CRT34.
摘要翻译：目的：为了能够通过毛刺检测装置从输入逻辑信号检测到毛刺的方法来识别包含的数据，并且通过字符显示控制装置控制包含毛刺的输入信号的字符的显示。构成：来自探针10的输入逻辑信号中的数据分量和毛刺分量由相应的存储器电路14,18通过块12存储，并且当从键盘30输入显示顺序时，CPU24将存储器内容存储电路14,18至RAM28基于ROM26的坚固磨损。此外，由RAM28存储由键盘30选择的显示模式和显示区域信息，并且显示控制电路32重复读取RAM28的显示RAM区域的内容以通过CRT34显示逻辑状态。

30. 发明专利

JPS53128258A AD CONVERTER 失效
公开(公告)号：JPS53128258A
公开(公告)日：1978-11-09
申请号：JP4306577
申请日：1977-04-14
申请人： SONY TEKTRONIX CORP
发明人： MUROOKA RIKICHI
IPC分类号： H03M1/14 , H03M1/36

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