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1. 发明专利

JPH06273489A DIGITAL PATTERN GENERATOR 失效
公开(公告)号：JPH06273489A
公开(公告)日：1994-09-30
申请号：JP8561193
申请日：1993-03-19
申请人： SONY TEKTRONIX CORP
发明人： IWASA TETSUO , HORISHITA YOSHIKUNI
IPC分类号： G01R31/3183 , G01R31/28
摘要： PURPOSE:To enable independent timing waveforms to be outputted from respective channels with a small scale of circuit in spite of multichannel. CONSTITUTION:A pattern stored in a timing RAM 64 is read out by timing clock faster than data clock, operated by an operating means 80 along with data pattern read out from a pattern memory 20 according to data clock, and outputted as a timing waveform. Therefore, by storing necessary patterns in the timing RAM 64, most of timing waveforms necessary to timing analysis can be formed.

2. 发明专利

JPS59223987A STORAGE DEVICE OF DIGITAL SIGNAL 失效
公开(公告)号：JPS59223987A
公开(公告)日：1984-12-15
申请号：JP9312383
申请日：1983-05-26
申请人： SONY TEKTRONIX CORP
发明人： MUROOKA RIKICHI , KOYAMA TETSUO , TSUKAMOTO TAKUROU , IWASA TETSUO , TAKAHASHI HISAO , KURATA MAKOTO
IPC分类号： G11B20/10 , G06F12/06 , G06F12/08 , G11C7/00 , G11B5/09 , G11C9/06
摘要： PURPOSE:To obtain a high-speed and large-capacity digital signal storage device by using N (N is an integer of >=3) pieces of serial-input serial-output type shift registers as high-speed small-capacity storage elements, and memories, such as RAM, etc., as low-speed large-capacity storage elements. CONSTITUTION:After writing is completed, each shift register 12-1-12-4 successively sends digital signals stored by means of the 2nd clock signal, whose frequency is lower than that of the 1st clock signal, to corresponding memories. Namely, of the N pieces shift registers only one shift register is in the writing operation and the others are in the reading out operation. Since the N is an integer of >=3, only 1/(N-1) of the writing speed is sufficient for the reading out speed of each shift register and the writing speed of the memories can be delayed by the amount. Moreover, since outputs of the shift registers are supplied to the memories 18-1-18-4 without passing through storage elements, such as latch circuit, etc., a low reading out speed obtained by the combination of the shift registers can be applied to the writing speed of the memories under the same condition. Therefore, an efficient high-speed large-capacity digital signal storage device is obtained when compared with conventional techniques.

3. 发明专利

JPS6329357B2 失效
公开(公告)号：JPS6329357B2
公开(公告)日：1988-06-13
申请号：JP9312383
申请日：1983-05-26
申请人： SONY TEKTRONIX CORP
发明人： MUROOKA RIKICHI , KOYAMA TETSUO , TSUKAMOTO TAKURO , IWASA TETSUO , TAKAHASHI HISAO , KURATA MAKOTO
IPC分类号： G11B20/10 , G06F12/06 , G06F12/08 , G11C7/00

4. 发明专利

JPH058987B2 失效
公开(公告)号：JPH058987B2
公开(公告)日：1993-02-03
申请号：JP13556786
申请日：1986-06-11
申请人： SONY TEKTRONIX CORP
发明人： IWASA TETSUO
IPC分类号： G01R13/20 , G01R13/28

5. 发明专利

JPH0495277A DEFECT DETECTING DEVICE FOR MAGNETIC RECORDING MEDIUM 失效
公开(公告)号：JPH0495277A
公开(公告)日：1992-03-27
申请号：JP21345490
申请日：1990-08-10
申请人： SONY TEKTRONIX CORP
发明人： IWASA TETSUO
IPC分类号： G11B20/18 , G11B5/00 , G11B5/84
摘要： PURPOSE:To exactly execute the error detection without complicating the circuit configuration by detecting an error by using a write clock synchronized with a reproducing signal, in the case a detecting signal of a zero crossing point does not exist. CONSTITUTION:The device is provided with a zero crossing detecting circuit 304 for detecting a zero crossing point from a reproducing from a reproducing signal from a magnetic recording medium in which write data is recorded by synchronizing with a write clock WCLK, a voltage comparing circuit for compar ing the reproducing signal with a reference voltage, and an error detecting circuit 302 for detecting an error of the reproducing signal, based on output signals of the zero crossing detecting circuit and the voltage comparing circuit. In such a state, when the zero crossing point is not detected from the reproduc ing signal by the zero crossing detecting circuit, in the error detecting circuit, the write clock WCLK is used instead of a detecting signal of the zero crossing point. That is the write clock is a stable clock, and also, becomes a signal synchronized with the reproducing signal. In such a way, the error detection can be executed exactly without complicating the circuit configuration.

6. 发明专利

JPS62291572A SIGNAL MEMORY MEASURING APPARATUS 失效
公开(公告)号：JPS62291572A
公开(公告)日：1987-12-18
申请号：JP13556786
申请日：1986-06-11
申请人： SONY TEKTRONIX CORP
发明人： IWASA TETSUO
IPC分类号： G01R13/20 , G01R13/28
摘要： PURPOSE:To simply know a memory position, by extending the bit period of an input digital signal using a series/parallel converter circuit and a latch circuit. CONSTITUTION:A first series/parallel converter circuit 38 converting a DC digital signal to N (N is an integer of 2 or more)-bit parallel digital signals, a latch circuit 44 latching the parallel digital signal from the circuit 38, a memory circuit 50 storing the parallel digital signal from the circuit 44 and a second series/parallel converter circuit 40 receiving the output signals of trigger circuits 26-32 to convert the same to N-bit parallel digital signals are provided. At every N bits of digital signals corresponding to an input signal, the N clock components of the digital signals are simultaneously stored in the memory circuit 50. Therefore, from the output state from the circuit 40 when a trigger point is detected, the bit among the bits of the parallel digital signals of the circuit 3 corresponding to the bit of the trigger point is cleared. As a result, from the output state of the circuit 40 when the trigger point is detected and the address signal of an address counter 62, the memory position of the circuit 50 corresponding to the trigger point is made clear.

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