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1. 发明专利

JPWO2017081759A1 Ａ／Ｄ変換装置审中-公开
公开(公告)号：JPWO2017081759A1
公开(公告)日：2018-03-15
申请号：JP2017549911
申请日：2015-11-11
申请人：三菱電機株式会社
发明人：小林悠介 , 生川貴康 , 恒岡雅也 , 船越政行 , 山口敦弘 , 岡上卓弘
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/10 , H03M1/12
摘要：対象物(4,5)のアナログ電気量を1つずつ独立にA/D変換器(1)へ出力する第1のモードと、対象物(4,5)のアナログ電気量を全て出力しない第2のモードと、対象物(4,5)のアナログ電気量を全て出力せず、かつA/D変換器(1)への出力をプルダウン抵抗(10)によりプルダウンさせる第3のモードと、対象物(4,5)のアナログ電気量を複数同時にA/D変換器(1)へ出力する第4のモードと、を発生させ、前記第1のモードの時に対象物(4,5)のA/D変換値を個別に取得し、前記第2モードから第4モードの時に、A/D変換器(1)自体、またはA/D変換器(1)に接続される装置の異常を検出する。

2. 发明专利

JPWO2017018140A1 車載制御装置、車載集積回路审中-公开
公开(公告)号：JPWO2017018140A1
公开(公告)日：2017-11-16
申请号：JP2017531106
申请日：2016-07-06
申请人：日立オートモティブシステムズ株式会社
发明人：洋一郎小林 , 洋一郎小林 , 理仁曽根原 , 理仁曽根原
IPC分类号： G06F11/22 , B60R16/02 , H01L21/822 , H01L27/04 , H03M1/10
CPC分类号： B60R16/02 , G01R31/28 , G06F11/22 , H01L21/822 , H01L27/04 , H03M1/10
摘要：出荷後も継続的に安定した出力値を出力することができる半導体集積回路およびそれを用いた車載制御装置を提供する。本発明は、基準信号を出力する基準信号発生部を備え、前記基準信号発生部が異なる2時点において出力した前記基準信号それぞれに対応する半導体回路の出力値間の差分に基づき、前記半導体回路の動作状態を検出する。

3. 发明专利

JP2014150338A Sensor signal processing device and sensor device 有权
标题翻译：传感器信号处理装置和传感器装置
公开(公告)号：JP2014150338A
公开(公告)日：2014-08-21
申请号：JP2013016878
申请日：2013-01-31
申请人： Denso Corp , 株式会社デンソー
发明人： TANIZAWA YUKIHIKO
IPC分类号： H03M1/08 , H03M1/10
CPC分类号： H03M1/0609 , G01D3/0365 , G01K7/16 , H03M1/10 , H03M1/462
摘要： PROBLEM TO BE SOLVED: To shorten a time from the start of A/D conversion of a sensor signal to the output of A/D conversion data with temperature characteristics of a physical quantity sensor canceled.SOLUTION: A sensor signal processing device includes a first A/D converter 7 having a variable offset and conversion gain and configured to A/D-convert a sensor signal of a physical quantity sensor 2, and a second A/D converter 8 configured to A/D-convert a temperature signal of a temperature sensor 3 for sensing a temperature of the physical quantity sensor 2. A temperature measurement process of instructing the A/D converter 8 to execute A/D conversion of the temperature signal, an arithmetic process of computing such an offset and conversion gain of the A/D converter 7 so as to cancel temperature characteristics of the physical quantity sensor 2 in the process of the A/D converter 7 A/D-converting the sensor signal, on the basis of an A/D conversion value of the A/D converter 8 and temperature characteristic data on the physical quantity sensor 2, and a signal conversion process of setting the computed offset and conversion gain in the A/D converter 7 to instruct the A/D converter 7 to execute A/D conversion of the sensor signal are executed concurrently.
摘要翻译：要解决的问题：缩短从传感器信号的A / D转换开始到取消物理量传感器的温度特性的A / D转换数据的输出的时间。解决方案：传感器信号处理装置包括第一 A / D转换器7，其具有可变的偏移和转换增益，并且被配置为对物理量传感器2的传感器信号进行A / D转换;以及第二A / D转换器8，被配置为对温度传感器3，用于感测物理量传感器2的温度。指示A / D转换器8执行温度信号的A / D转换的温度测量处理，计算该温度信号的偏移和转换增益的运算处理 A / D转换器7，以在A / D转换器7的处理中消除物理量传感器2的温度特性，A / D转换器根据A / D转换器的A / D转换值， D转换器8和温度执行物理量传感器2的特征特征数据以及在A / D转换器7中设定计算出的偏移和转换增益以指示A / D转换器7执行传感器信号的A / D转换的信号转换处理同时。

4. 发明专利

JP4299257B2 Zero point correction circuit of the load meter 有权
公开(公告)号：JP4299257B2
公开(公告)日：2009-07-22
申请号：JP2005065306
申请日：2005-03-09
申请人：株式会社理研オプテック
发明人：弘行森谷
IPC分类号： B30B15/28
CPC分类号： G01L5/0066 , G01L1/2268 , G01L5/0076 , H03M1/10

5. 发明专利

JP2006313162A System and method for calibrating time interleaved timing of data converter 审中-公开
标题翻译：用于校准数据转换器的时间间隔时序的系统和方法
公开(公告)号：JP2006313162A
公开(公告)日：2006-11-16
申请号：JP2006128483
申请日：2006-05-02
申请人： Agilent Technol Inc , アジレント・テクノロジーズ・インクAgilent Technologies, Inc.
发明人： FERNANDEZ ANDREW D , SRIKANTAM VAMSI K , NEFF ROBERT M R , POULTON KENNETH D
IPC分类号： G01R35/00 , H03M1/12
CPC分类号： H03M1/10 , H03M1/1205 , H03M1/662
摘要： PROBLEM TO BE SOLVED: To provide system and method for faster and low-cost calibration of sampling timing in data conversion system.
SOLUTION: This is the method for calibrating time-interleaved sample, comprising a step (102) for impressing calibration signal on time-interleaved sampling device, a step (104) for sampling calibration signal in multiphase by using the time-interleaved sampling device to produce a plurality of samples, a step (106) for averaging those produced samples, and a step (108) for computing phase difference of each sample based on the average calibration signal sample. The calibration signal matches with at least one sampling clock in the sampling device, also being periodic to have prescribed spectral element and frequency.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供数据转换系统中采样定时更快更低成本校准的系统和方法。解决方案：这是用于校准时间交织样本的方法，包括用于在时间交织的采样装置上施加校准信号的步骤（102），用于通过使用时间交织的采样装置在多相中采样校准信号的步骤（104）采样装置以产生多个采样，用于平均那些产生的样本的步骤（106），以及用于基于平均校准信号样本计算每个样本的相位差的步骤（108）。校准信号与采样设备中的至少一个采样时钟相匹配，也是周期性地具有规定的频谱元素和频率。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JPS5917721A A/d conversion system 失效
标题翻译： A / D转换系统
公开(公告)号：JPS5917721A
公开(公告)日：1984-01-30
申请号：JP12672282
申请日：1982-07-22
申请人： Fuji Electric Co Ltd
发明人： YAMAMURO KIYOSHI , HERATSU SEIICHI
IPC分类号： H03M1/10
CPC分类号： H03M1/10
摘要： PURPOSE:To secure the time required for performing the converting operation plural times, by delaying the change of an analog input signal in the A/D conversion system which uses a digital operation controller and can be checked. CONSTITUTION:An A/D converter 2 is allowed to perform the converting operation plural times, and the digital value obtained each time is judged to be correct and is stored when the preceding value of upper prescribed number of bits of this digital value and the current value of that coincide with each other at least, thereby improving the reliability of data. A simple means which delays or integrates the input analog signal is added to an operational amplifier 1 to secure easily the time required for executing the converting operation plural times.
摘要翻译：目的：通过延迟使用数字操作控制器的A / D转换系统中的模拟输入信号的变化，可以多次确保执行转换操作所需的时间，并且可以进行检查。构成：允许A / D转换器2进行多次转换操作，并且每次获得的数字值被判断为正确，并且当该数字值的上限规定位数的前一值和当前值值至少彼此一致，从而提高数据的可靠性。将运算放大器1添加到延迟或积分输入模拟信号的简单装置，以便容易地确保多次执行转换操作所需的时间。

7. 发明专利

JPS59127417A Digital-analog converter 失效
标题翻译：数字模拟转换器
公开(公告)号：JPS59127417A
公开(公告)日：1984-07-23
申请号：JP270183
申请日：1983-01-11
申请人： Yamatake Honeywell Co Ltd
发明人： MOCHIZUKI KIYOSHI
IPC分类号： H03M1/10
CPC分类号： H03M1/10
摘要： PURPOSE:To provide a feedback inspecting function for an output current and to simplify constitution by feeding back the output of a counter. CONSTITUTION:The amplitude and frequency of a digital signal from a processor CPU are varied to extract a necessary analog signal by a filter FL1. A comparator CMP compares it with the output signal of an output buffer circuit OBF and sends the result to a counter CNT. The counter CNT varies in counted value by the output based upon the comparison output, and the counted value is supplied to the CPU and also inputted to the 2nd D/A converter D/A2 to vary the amplitude and frequency, so that a necessary analog signal appears at its output. The output buffer circuit OBF controls a transistor to send the output signal to the other input terminal of the comparator CMP. Thus, a digital controller checks the actual analog current output value.
摘要翻译：目的：提供输出电流的反馈检测功能，并通过反馈计数器的输出来简化结构。构成：改变来自处理器CPU的数字信号的幅度和频率，以通过滤波器FL1提取必要的模拟信号。比较器CMP将其与输出缓冲器电路OBF的输出信号进行比较，并将结果发送到计数器CNT。计数器CNT根据比较输出以计数值变化输出，并将计数值提供给CPU，并且还输入到第二D / A转换器D / A2以改变幅度和频率，使得必要的模拟信号出现在其输出端。输出缓冲电路OBF控制晶体管将输出信号发送到比较器CMP的另一个输入端。因此，数字控制器检查实际的模拟电流输出值。

8. 发明专利

JPS59123314A System for checking analog-digital conversion 失效
标题翻译：检查模拟数字转换系统
公开(公告)号：JPS59123314A
公开(公告)日：1984-07-17
申请号：JP23194282
申请日：1982-12-29
申请人： Fujitsu Ltd
发明人： YUI MITSURU , NOZAWA KUNIO
IPC分类号： H03M1/10
CPC分类号： H03M1/10
摘要： PURPOSE:To simplify the check operation by providing an analog signal level detecting section to a device converting a detected analog signal into a digital signal and transmitting the converted signal so as to check the A/D converting operation when no output of this detecting section exists. CONSTITUTION:A waveform remote transmitter 30 detecting an analog signal such as earthequake wave or the like, converting it into a digital signal and transmitting the signal to a receiver of a master station, has an A/D converting section 11, a parallel serial converting section 12, a control section 13, a level detecting section 31 and a timer section 32. The analog signal such as earthquake wave or the like is inputted to the A/D converting section and the level detecting section 31. The level detecting section 31 outputs a pulse to the timer section 32 to an input of a prescribed level or over. The timer section 32 applies an output pulse to the control section 13 during a prescribed time after an input is applied. The control section 13 switches the input of the A/D converting section 11 to a power supply 15 for check when no pulse is inputted from the timer section.
摘要翻译：目的：为了简化检查操作，将模拟信号电平检测部分提供给将检测到的模拟信号转换为数字信号的装置，并发送转换的信号，以便当该检测部分的输出不存在时检查A / D转换操作。构成：检测诸如三次方波等的模拟信号的波形远程发送器30将其转换为数字信号并将信号发送到主站的接收机，具有A / D转换部分11，并行串行转换部分12，控制部分13，电平检测部分31和定时器部分32.诸如地震波等的模拟信号被输入到A / D转换部分和电平检测部分31.电平检测部分31 将定时器部分32的脉冲输出到规定级别以上的输入。定时器部分32在施加输入之后的规定时间期间向控制部分13施加输出脉冲。当没有从定时器部分输入脉冲时，控制部分13将A / D转换部分11的输入切换到用于检查的电源15。

9. 发明专利

JPS5972222A A/d converting device 失效
标题翻译： A / D转换器件
公开(公告)号：JPS5972222A
公开(公告)日：1984-04-24
申请号：JP18230482
申请日：1982-10-18
申请人： Nec Corp
发明人： NISHIZAWA TATSUO
IPC分类号： H03M1/18 , H03M1/10
CPC分类号： H03M1/10
摘要： PURPOSE:To prevent an overflow and to perform invariably optimum A/D conversion by converting an input signal into a stepwise output, comparing it with a set level and suppressing the output level within a specific range, and then converting it into a digital signal. CONSTITUTION:The input analog signal 1 is converted into the stepwise output 6 which holds a specific value during a sampling period by a sample holding device 2. Then, the output 6 is compared by a multiplication magnification controller 3 with a previously set level to decide on magnification so that the output 7 of a multiplier 4 is between output levels + or -V. Then, the output 7 is inputted to an A/D converter 5 which inputs + or -V as full-scale inputs to obtain the output digital signal 8.
摘要翻译：目的：为了防止溢出，并通过将输入信号转换为逐步输出，将其与设定电平进行比较，并抑制特定范围内的输出电平，然后将其转换为数字信号，从而实现最佳的A / D转换。构成：输入模拟信号1被转换成逐步输出6，其在采样期间由采样保持装置2保持特定值。然后，输出6被倍增控制器3与先前设定的电平进行比较，以决定放大倍率使得乘法器4的输出7在输出电平+或-V之间。然后，将输出7输入到输入+或-V作为满量程输入的A / D转换器5，以获得输出数字信号8。

10. 发明专利

JPS5967721A Lsi for analog-digital conversion 失效
标题翻译：用于模拟数字转换的LSI
公开(公告)号：JPS5967721A
公开(公告)日：1984-04-17
申请号：JP17742882
申请日：1982-10-08
申请人： Shiojiri Kogyo Kk
发明人： TEZUKA MUTSUTO
IPC分类号： G01R15/12 , H03M1/10
CPC分类号： H03M1/10
摘要： PURPOSE:To provide additionally a diode check function without cost increase by designing a low open voltage of a measuring terminal at resistor measurement, incorporating a discriminating circuit for conduction/nonconduction of diodes and making an open voltage at the resistance measurement terminal equal to a power supply voltage at its function. CONSTITUTION:Switches 40, 41 are turned on and switches 12-15 are turned off at the diode check function. A VDD potential is given to the resistance measurement terminal through the switch 40, a reference resistor 8 and a resistor 4 in this case. In connecting a diode 20 to the measuring terminal as shown in Figure, the forward voltage VF is split with resistors 6, 42 and the result is a voltage within the measuring range of OMEGAVx. When the diode 20 is placed in the opposite direction, the VDD is split with the resistors 6, 42 in place of the VF and given to the OMEGAVx. The switching 40, 41 formed in the LSI have resistance of 5,000MOMEGA-10,000MOMEGA, then insulation is out of question and the same protection circuit as the resistance measuring circuit is used.
摘要翻译：目的：通过在电阻测量时设计测量端子的低开路电压，提供额外的二极管检查功能，无需增加成本，并入二极管的导通/非导通识别电路，并使电阻测量端子处的开路电压等于功率电源电压在其功能。构成：在二极管检查功能下，开关40,41接通，开关12-15断开。在这种情况下，通过开关40，参考电阻8和电阻4向电阻测量端子施加VDD电位。在将二极管20连接到如图所示的测量端子时，正向电压VF与电阻器6,42分开，结果是在OMEGAVx的测量范围内的电压。当二极管20处于相反方向时，VDD与电阻器6,42分开代替VF并被赋予OMEGAVx。在LSI中形成的开关40,41具有5000MOMEGA-10,000MOMEGA的电阻，因此绝缘不成问题，并且使用与电阻测量电路相同的保护电路。

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