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11. 发明专利

JP2008047904A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008047904A
公开(公告)日：2008-02-28
申请号：JP2007208713
申请日：2007-08-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , TANAKA TOSHIHIKO , YAMANAKA TOSHIAKI , SAKATA TAKESHI , KIMURA KATSUTAKA
IPC分类号： H01L21/8242 , G03F1/00 , G03F1/68 , G03F7/20 , G11C11/401 , H01L21/027 , H01L21/82 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/112 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a pattern that can solve problems of short-circuit or breaking of word lines and data line ends caused by interference of diffracted light produced at a pattern end on a boundary part between a memory array and a sub-word driver or sense amplifier when fine word lines and data lines having linewidth smaller than a wavelength are patterned on a memory. SOLUTION: In a mask pattern (a) for patterning word lines and data lines, lengths of word lines WL1, WL2, WL5 and WL6 having end parts neighboring each other are varied to shift their ends from each other, and further the ends of word lines WL1, WL2, WL5 and WL6 are slanted. Separation within a resist pattern and contact of patterns with each other can be thereby prevented, and also breakage of wires to be patterned and short-circuiting between wires can be prevented. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成图案的方法，该图案可以解决由在图案端处产生的衍射光的干涉引起的字线和数据线端的短路或断裂的问题，存储器阵列和子字驱动器或读出放大器，当具有小于波长的线宽的细字线和数据线被图案化时。解决方案：在用于构图字线和数据线的掩模图案（a）中，改变具有彼此相邻的端部的字线WL1，WL2，WL5和WL6的长度，以使其端部彼此偏移，字线WL1，WL2，WL5和WL6的端部是倾斜的。因此可以防止抗蚀剂图案之间的分离和图案彼此的接触，并且可以防止图案化的电线断裂和电线之间的短路。版权所有（C）2008，JPO＆INPIT

12. 发明专利

JP2007067451A Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2007067451A
公开(公告)日：2007-03-15
申请号：JP2006333044
申请日：2006-12-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIMURA SHINICHIRO , YAMANAKA TOSHIAKI , ITO KIYOO , SAKATA TAKESHI , SEKIGUCHI TOMONORI , MATSUOKA HIDEYUKI
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which solves problems of a prior art three-dimensional memory cell and provides size of more minute, and the manufacturing method thereof. SOLUTION: In a trench formed through dielectric films (6, 8, 10 and 12) laminated on a semiconductor substrate (1), a capacitor composed of a storage electrode (19), a capacitor dielectric film (20), and a plate electrode (21) is formed, and buried wiring layers (9 and 11) are formed below the capacitor. Since the capacitor is formed not in the semiconductor substrate but above it, there is a room of area where the capacitor can be formed, and by using the wiring layers (9 and 11) as a global word line and a selector line, the difficulty of forming wiring is reduced. Moreover, since the upper surface of a dielectric film (32) being in contact with the lower surface of wiring (34) of a peripheral circuit region, extends to a memory cell region so as to be in contact with the side of the capacitor (33), a step height between the peripheral circuit region and the memory cell region is remarkably reduced. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种解决现有技术的三维存储单元的问题并提供更多分辨率的半导体存储器件及其制造方法。解决方案：在通过层压在半导体衬底（1）上的电介质膜（6,8,10和12）形成的沟槽中，形成由存储电极（19），电容器电介质膜（20）和形成了平板电极（21），在电容器的下方形成有掩埋布线层（9,11）。由于电容器不是形成在半导体衬底中并且在其上方，所以存在可以形成电容器的区域的空间，并且通过使用布线层（9和11）作为全局字线和选择线，难度的布线减少。此外，由于与周边电路区域的布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域，以与电容器的一侧接触 33），外围电路区域和存储单元区域之间的台阶高度显着降低。版权所有（C）2007，JPO＆INPIT

13. 发明专利

JP2002368126A Production method for semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备的生产方法
公开(公告)号：JP2002368126A
公开(公告)日：2002-12-20
申请号：JP2001176472
申请日：2001-06-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMANAKA TOSHIAKI , NISHIDA AKIO , YOSHIDA YASUKO , IKEDA SHUJI , KURODA KENICHI , KANBARA SHIRO , KIMURA SHINICHIRO , MURAKAMI HIDEKAZU , MATSUOKA HIDEYUKI , MINAMI MASATAKA
IPC分类号： H01L27/092 , H01L21/265 , H01L21/266 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/2652 , H01L21/823842 , H01L21/823892
摘要： PROBLEM TO BE SOLVED: To solve the problem of production costs increasing due to increased production processes, since photomasks are required as many as the number of kinds of wells, channels stoppers, gate electrodes and ion implantations for threshold control or the like.
SOLUTION: Areas for NMIS of a low Vth and PMIS of a high Vth are set, by using a photoresist mask for forming the well as well, and the regions for the NMIS of high Vth and the PMIS of low Vth are set through one ion implantation process by the photoresist mask of a opening part common to the NMIS and the PMIS. Also, after oxidizing of the gate, ion implantation to the well, channel and the gate electrode are performed through a noncrystalline silicon film. Therefore, setting of the threshold voltage for a plurality of CMIS or gate electrodes of both polarities can be provided by fewer photoresist processes.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了解决由于生产工艺的增加而导致的生产成本增加的问题，由于光掩模需要孔数，通道挡块，栅电极和用于阈值控制的离子注入等的数量。解决方案：通过使用用于形成阱的光致抗蚀剂掩模来设置具有高Vth的低Vth和PMIS的NMIS的区域，并且通过一个离子设置高Vth的NMIS的区域和低Vth的NMIS的区域通过NMIS和PMIS共同的开口部分的光刻胶掩模进行注入工艺。此外，在栅极氧化之后，通过非晶硅膜进行到阱，沟道和栅电极的离子注入。因此，可以通过较少的光刻胶工艺来提供两个极性的多个CMIS或栅电极的阈值电压的设置。

14. 发明专利

JP2000077531A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2000077531A
公开(公告)日：2000-03-14
申请号：JP24802698
申请日：1998-09-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMANAKA TOSHIAKI , SEKIGUCHI TOMONORI , SAKATA TAKESHI , KIMURA SHINICHIRO , MATSUOKA HIDEYUKI
IPC分类号： H01L21/027 , G03F1/30 , G03F1/68 , H01L21/82 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which allows such a phase pattern arrangement that no gives rise to contradiction in the Levenson arrangement of a phase shifter, even at a part where an island-like wiring electrode pattern and a linear wiring electrode pattern are present, in the same wiring electrode layer formation mask.
SOLUTION: With a plurality of common gate electrodes 2 of a selective transistor provided for the pattern of wiring electrodes 4 and 5 of a plurality of signal lines connected to source/drain of each selective transistor to be a Levenson arrangement, adjoining active regions 1 forming each selective transistor are allocated so as to be alternately deviated in pair units. Thus, the Levenson arrangement is allowed for improved pattern density, resulting in a highly-integrated semiconductor integrated circuit device.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：为了提供一种半导体集成电路器件，即使在岛状布线电极图案和线性布线的一部分中也允许这样的相位图案布置，即不会引起移相器的列文森布莱斯矛盾的矛盾在相同的布线电极层形成掩模中存在电极图案。解决方案：通过选择晶体管的多个公共栅电极2，其设置为连接到每个选择晶体管的源极/漏极的多条信号线的布线电极4和5的图案为莱文森布置，邻接的有源区域1形成每个选择晶体管被分配成以成对的单位交替地偏离。因此，允许Levenson布置改善图案密度，从而形成高度集成的半导体集成电路器件。

15. 发明专利

JP2002213356A REFRIGERANT COMPRESSOR, AIR CONDITIONER AND REFRIGERATOR USING THE SAME, AND ITS BEARING 审中-公开
公开(公告)号：JP2002213356A
公开(公告)日：2002-07-31
申请号：JP2001328864
申请日：2001-10-26
申请人： HITACHI LTD , TOYO TANSO CO
发明人： TAKAYASU HIROSHI , BABA NOBORU , NAKAJIMA SHOICHI , TAGUCHI MASAMITSU , IIZUKA TADASHI , YAMANAKA TOSHIAKI , OHASHI MASABUMI , OGURA HIROAKI , FUKUDA TOSHIOMI , OZAKI SHINICHI
IPC分类号： F04B39/00 , F04C18/356 , F04C29/00 , F04C29/02 , F16C9/02
摘要： PROBLEM TO BE SOLVED: To provide a refrigerant compressor of long life using a bearing material having high abrasion resistance and seizure-resistance, and to provide an air conditioner and a refrigerator using the same, and its bearing. SOLUTION: In this compressor compressing the refrigerant by a pump driven by a crank of a rotating shaft, and repeating the liquefaction and evaporation for refrigerating, the air conditioner and the refrigerator using the same, and the bearing, at least one of bearings to the rotating shaft and the crank is made of a material prepared by impregnating pores of a carbonaceous base including graphite of 20-50 wt.%, with one kind of metal selected from the IB, VIII excluding Fe, and Sn, or an alloy mainly composed of the metal, the carbonaceous base includes graphite of 20-50 wt.%, Shore hardness of the member is 65-120, a porosity of the member is 0.05-2 vol.%, and the metal or the alloy of the member includes at least one of V and Ti by 2.0 wt.% or less.

16. 发明专利

JP2002124579A SEMICONDUCTOR DEVICE AND ITS FABRICATING METHOD 失效
公开(公告)号：JP2002124579A
公开(公告)日：2002-04-26
申请号：JP2000316964
申请日：2000-10-17
申请人： HITACHI LTD
发明人： MURAKAMI HIDEKAZU , NISHIDA AKIO , UMEDA KAZUNORI , OKUYAMA KOSUKE , YAMANAKA TOSHIAKI , YOSHIGAMI JIRO , KIMURA SHINICHIRO
IPC分类号： H01L29/43 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device where an MISFET having a thin gate insulation film and an MISFET having a thick gate insulation film exist mixedly and hot carrier resistance of the MISFET having a thick gate insulation film is enhanced. SOLUTION: The method for fabricating a semiconductor device comprises a step for forming a thick gate oxide film (thick oxide film) 14 in the first region of a substrate 10 and a thin gate oxide film (thin oxide film) 15 in the second region thereof and then oxidizing/nitriding these gate oxide films 14 and 15, a step for forming gate electrodes 1a-1d on these gate oxide films 14 and 15, and a step for forming a high oxidation/nitridation region 112 at at least a part of the interface between the thick gate oxide film (thick oxide film) 14 and the substrate 10 before or after forming the gate electrodes 1a-1d.

17. 发明专利

JPH1079478A DYNAMIC RAM DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1079478A
公开(公告)日：1998-03-24
申请号：JP23427296
申请日：1996-09-04
申请人： HITACHI LTD
发明人： YAMANAKA TOSHIAKI , KIMURA SHINICHIRO , ITO KIYOO , MATSUOKA HIDEYUKI , SEKIGUCHI TOMONORI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve resistance with respect to soft error and reliability by increasing the depth of a trench of a solid capacitor for charge storage, formed at a position higher than a substrate upper surface. SOLUTION: A switch transistor is an n-channel type MISFET formed in a region on a p-type silicon substrate 1 isolated with a field oxide film 2, and a gate electrode 4 is a word line on an active region. A wiring electrode 8 is a data line connected to a high-concentration n-type impurity region 5 of a source (or drain) of the switch transistor. Further, a storage electrode 12 of the capacitor for charge storage is provided at the upper ends of the word line and the data line. The storage electrode 12 is connected to a high- concentration n-type impurity region 6 of the MISFET in the memory cell via a silicon plug 10. The storage electrode 12, formed in a trench shape, includes a rectangular-parallelepiped plate electrode 14 via a capacitor insulating film 13 which is between the inner wall of the electrode 12 and the plate electrode 14.

18. 发明专利

JPH1022471A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1022471A
公开(公告)日：1998-01-23
申请号：JP17328096
申请日：1996-07-03
申请人： HITACHI LTD
发明人： YAMANAKA TOSHIAKI , KIMURA SHINICHIRO , ITO KIYOO , SAKATA TAKESHI , SEKIGUCHI TOMONORI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a capacitor of a three-dimensional structure with high reliability and high density, such as, a DRAM (dynamic random access memory) cell. SOLUTION: Trench capacitors 3, 4 are provided in a substrate, and a thin- film silicon layer 8 is formed on an insulating film 5 on the upper part of the trench capacitors by bonding and film thinning steps. A switch transistor is provided in the thin-film silicon layer, and a conductor 6 for connecting a high- concentration impurity region 12 of a source or drain of the trench capacitor with a storage electrode 4 of the switch transistor is provided in the insulating film 5. Thus, in the case where a DRAM cell is constituted, since a capacitor having a large occupied area and a large storage capacitance may be easily formed on a memory cell, an inexpensive, high-density semiconductor memory device may be realized.

19. 发明专利

JPH09246487A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH09246487A
公开(公告)日：1997-09-19
申请号：JP5132996
申请日：1996-03-08
申请人： HITACHI LTD
发明人： HIRAIWA ATSUSHI , KIMURA SHINICHIRO , YAMANAKA TOSHIAKI
IPC分类号： G11C11/402 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To extend the refresh period by making the absolute value of voltage that is given previously to a data line before reading stored information lower than a half of the absolute value of the voltage for the writing information. SOLUTION: A gate oxide film 2 and a gate electrode 3 are formed on a p type well 1 after forming an element separating oxide film 9 on it. A first layer insulating film 4 is formed and a capacitor is completed by forming an accumulating electrode 6, a capacitor insulating film 7 and a plate electrode 8. A data line 14 is formed after forming a second layer insulating film 13. A depletion layer 10 is formed directly under and around the gate oxide film 10 and diffusion layers 11 and 5. With this, the hold time of data is extended and the power consumption of a DRAM can be reduced.

20. 发明专利

JPH08316339A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08316339A
公开(公告)日：1996-11-29
申请号：JP13162596
申请日：1996-05-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , SHIMIZU AKIHIRO , ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , TAKEDA EIJI
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
摘要： PURPOSE: To obtain a semiconductor memory in which a novel static random access memory cell having reduced occupation area is fabricated on a semiconductor substrate. CONSTITUTION: The word line in a memory cell comprises a pair of word lines 11a, 11d extending along a first direction on the major surface of a semiconductor substrate while being spaced apart from each other. The gate 11b, 11c of insulated gate FET T1, T2 for driving extends longitudinally along the first direction on the major surface of a semiconductor substrate between the word lines 11a, 11d and a pair of load elements, i.e., insulated gate FETs, are arranged above the gates of the transistors T1, T2. Since the gate of a transistor, i.e., a load element, is arranged on each transistor T1, T2, the occupation area of memory cell can be reduced significantly.

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