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1. 发明专利

JP2010267373A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010267373A
公开(公告)日：2010-11-25
申请号：JP2010151546
申请日：2010-07-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HANZAWA SATORU , SAKATA TAKESHI , MATSUOKA HIDEYUKI
IPC分类号： G11C11/15 , G11C29/04 , G11C5/00 , G11C7/00 , G11C11/00 , G11C11/16 , G11C11/34 , H01L27/22 , H01L31/0328
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： PROBLEM TO BE SOLVED: To provide a reference signal generation method and a dummy cell for use in a reading operation of a memory cell storing information by utilizing a change of a magnetic resistance. SOLUTION: The following are included: a plurality of first memory cells MC provided at intersections between a plurality of word lines WR0-WR7 and a plurality of first data lines D0-D7, for storing either "1" or "0"; a plurality of first dummy cells MCH provided at intersections between the plurality of word lines WR0-WR7 and a first dummy data line DD0, for storing "1"; and a plurality of second dummy cells MCL provided at intersections between the plurality of word lines WR0-WR7 and a second dummy data line DD1, for storing "0". Information is written to the first and second dummy cells using a write circuit in a manner similar to that for the plurality of memory cells. A large capacity MRAM having a higher integration density and higher reliability as compared with the conventional one is achieved. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过利用磁阻的变化来存储信息的存储单元的读取操作中使用的参考信号产生方法和虚拟单元。包括以下内容：多个第一存储单元MC，设置在多个字线WR0-WR7和多个第一数据线D0-D7之间的交叉处，用于存储“1”或“0” ; 设置在多个字线WR0-WR7和第一伪数据线DD0之间的交叉处的多个第一虚拟单元MCH，用于存储“1”; 以及设置在多个字线WR0-WR7和第二伪数据线DD1之间的交叉处的多个第二虚设单元MCL，用于存储“0”。以与多个存储单元相同的方式，使用写入电路将信息写入第一和第二虚设单元。实现了与传统的MRAM相比具有更高集成密度和更高可靠性的大容量MRAM。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2009123340A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009123340A
公开(公告)日：2009-06-04
申请号：JP2009058872
申请日：2009-03-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TAKESHI , OSADA KENICHI , TAKEMURA RIICHIRO , MATSUOKA HIDEYUKI
IPC分类号： G11C13/00
摘要： PROBLEM TO BE SOLVED: To achieve a highly integrated fast nonvolatile memory by enabling a stable operation of a phase-change memory in a short operation cycle time. SOLUTION: The semiconductor device includes a write data register DIR, an output data selector DOS, a write address register AR, an address comparator ACP, and a flag register FR. Write data is written in a memory cell, and held by the write data register until a next write cycle. If there is reading to its address during this period, reading to a memory cell array is stopped to read the data from the register. Without extending cycle time, writing time in a memory cell whose phase-change resistance is low, and a period from a writing operation for setting high phase-change resistance to a reading operation in the memory are extended. As a result, a stable writing operation is carried out. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在短的操作周期时间内实现相变存储器的稳定操作来实现高度集成的快速非易失性存储器。解决方案：半导体器件包括写数据寄存器DIR，输出数据选择器DOS，写地址寄存器AR，地址比较器ACP和标志寄存器FR。写数据写入存储单元，并由写数据寄存器保持，直到下一个写周期。如果在此期间读取其地址，则停止对存储单元阵列的读取以从寄存器读取数据。没有延长周期时间，写入时间在相变电阻低的存储单元中，并且延长了用于设置高相变电阻到存储器中的读取操作的写入操作的周期。结果，执行稳定的写入操作。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008047904A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008047904A
公开(公告)日：2008-02-28
申请号：JP2007208713
申请日：2007-08-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , TANAKA TOSHIHIKO , YAMANAKA TOSHIAKI , SAKATA TAKESHI , KIMURA KATSUTAKA
IPC分类号： H01L21/8242 , G03F1/00 , G03F1/68 , G03F7/20 , G11C11/401 , H01L21/027 , H01L21/82 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/112 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a pattern that can solve problems of short-circuit or breaking of word lines and data line ends caused by interference of diffracted light produced at a pattern end on a boundary part between a memory array and a sub-word driver or sense amplifier when fine word lines and data lines having linewidth smaller than a wavelength are patterned on a memory. SOLUTION: In a mask pattern (a) for patterning word lines and data lines, lengths of word lines WL1, WL2, WL5 and WL6 having end parts neighboring each other are varied to shift their ends from each other, and further the ends of word lines WL1, WL2, WL5 and WL6 are slanted. Separation within a resist pattern and contact of patterns with each other can be thereby prevented, and also breakage of wires to be patterned and short-circuiting between wires can be prevented. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成图案的方法，该图案可以解决由在图案端处产生的衍射光的干涉引起的字线和数据线端的短路或断裂的问题，存储器阵列和子字驱动器或读出放大器，当具有小于波长的线宽的细字线和数据线被图案化时。解决方案：在用于构图字线和数据线的掩模图案（a）中，改变具有彼此相邻的端部的字线WL1，WL2，WL5和WL6的长度，以使其端部彼此偏移，字线WL1，WL2，WL5和WL6的端部是倾斜的。因此可以防止抗蚀剂图案之间的分离和图案彼此的接触，并且可以防止图案化的电线断裂和电线之间的短路。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007067451A Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2007067451A
公开(公告)日：2007-03-15
申请号：JP2006333044
申请日：2006-12-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KIMURA SHINICHIRO , YAMANAKA TOSHIAKI , ITO KIYOO , SAKATA TAKESHI , SEKIGUCHI TOMONORI , MATSUOKA HIDEYUKI
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which solves problems of a prior art three-dimensional memory cell and provides size of more minute, and the manufacturing method thereof. SOLUTION: In a trench formed through dielectric films (6, 8, 10 and 12) laminated on a semiconductor substrate (1), a capacitor composed of a storage electrode (19), a capacitor dielectric film (20), and a plate electrode (21) is formed, and buried wiring layers (9 and 11) are formed below the capacitor. Since the capacitor is formed not in the semiconductor substrate but above it, there is a room of area where the capacitor can be formed, and by using the wiring layers (9 and 11) as a global word line and a selector line, the difficulty of forming wiring is reduced. Moreover, since the upper surface of a dielectric film (32) being in contact with the lower surface of wiring (34) of a peripheral circuit region, extends to a memory cell region so as to be in contact with the side of the capacitor (33), a step height between the peripheral circuit region and the memory cell region is remarkably reduced. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种解决现有技术的三维存储单元的问题并提供更多分辨率的半导体存储器件及其制造方法。解决方案：在通过层压在半导体衬底（1）上的电介质膜（6,8,10和12）形成的沟槽中，形成由存储电极（19），电容器电介质膜（20）和形成了平板电极（21），在电容器的下方形成有掩埋布线层（9,11）。由于电容器不是形成在半导体衬底中并且在其上方，所以存在可以形成电容器的区域的空间，并且通过使用布线层（9和11）作为全局字线和选择线，难度的布线减少。此外，由于与周边电路区域的布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域，以与电容器的一侧接触 33），外围电路区域和存储单元区域之间的台阶高度显着降低。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005056452A Memory and semiconductor device 审中-公开
标题翻译：存储器和半导体器件
公开(公告)号：JP2005056452A
公开(公告)日：2005-03-03
申请号：JP2003205615
申请日：2003-08-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ATWOOD BRYAN , WATABE TAKAO , SAKATA TAKESHI
IPC分类号： H01L27/108 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/405 , G11C11/4093 , H01L21/8242 , H01L27/10
CPC分类号： G11C7/1039 , G11C7/1042 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C11/405 , G11C11/4093 , G11C2207/2281 , G11C2207/229 , H01L27/10885 , H01L27/10888
摘要： PROBLEM TO BE SOLVED: To improve the speed of write operation in a memory cell such as a 3-transistor cell in which writing acts as destructive operation.
SOLUTION: The memory is provided with a plurality of word lines WWL, RWL; a pair of data lines WDL, RDL which intersect a plurality of the word lines WWL, RWL; and memory columns including a plurality of memory cells MC prepared at the intersections of a plurality of the word lines WWL, RWL and the pair of data lines WDL, RDL, and each of the memory cells MC is accessible from a corresponding word line among the plurality of word lines WWL, RWL, and two lines of the word lines can be activated in parallel.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提高写入作为破坏性操作的诸如3晶体管单元的存储单元中的写入操作的速度。解决方案：存储器设置有多个字线WWL，RWL; 与多个字线WWL，RWL相交的一对数据线WDL，RDL; 并且包括在多个字线WWL，RWL和数据线对WDL，RDL以及每个存储单元MC的交叉处准备的多个存储单元MC的存储器列可从可以并行地激活多条字线WWL，RWL和字线的两行。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2004355691A Semiconductor device 审中-公开
公开(公告)号：JP2004355691A
公开(公告)日：2004-12-16
申请号：JP2003150246
申请日：2003-05-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HANZAWA SATORU , SAKATA TAKESHI , TAKEMURA RIICHIRO
IPC分类号： G11C5/00 , G11C15/04 , H01L21/8242 , H01L27/108
CPC分类号： G11C15/04 , G11C15/043
摘要： PROBLEM TO BE SOLVED: To realize an array having a high degree of integration while maintaining a proper retrieval speed in a T-CAM array which is constituted by a ternary dynamic CAM cell using a plurality of transistors by performing a refresh operation while reading stored information onto a match line employing a current path similar to the current path of a retrieval operation. SOLUTION: A rewrite data line, which is arranged in parallel with a match line, is arranged and a rewrite transistor is inserted between the rewrite data line and an accumulation node within a dynamic CAM cell. Having provided the above cell constitution, the refresh operation is realized by reading information stored in the accumulation node to the match line one at a time and writing the information from the rewrite data line. COPYRIGHT: (C)2005,JPO&NCIPI

7. 发明专利

JP2003264457A SEMICONDUCTOR INTEGRATED CIRCUIT HAVING POWER REDUCTION MECHANISM 审中-公开
公开(公告)号：JP2003264457A
公开(公告)日：2003-09-19
申请号：JP2003011747
申请日：2003-01-21
申请人： HITACHI LTD
发明人： HORIGUCHI SHINJI , UCHIYAMA KUNIO , ITO KIYOO , SAKATA TAKESHI , AOKI MASAKAZU , KAWAHARA TAKAYUKI
IPC分类号： H01L21/822 , G11C11/407 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/00 , H03K19/096 , H03K19/20
摘要： PROBLEM TO BE SOLVED: To provide a high speed/low power consumption semiconductor integrated circuit. SOLUTION: The semiconductor integrated circuit is provided with a first inverter circuit (L 41 ), latch circuits (L 42 , L 43 ) to be connected with the first inverter circuit (L 41 ) and a control circuit means (SC) to be connected with the first inverter circuit (L 41 ). The control circuit means (SC) is connected with the first inverter circuit (L 41 ), is supplied with a control signal, makes comparatively large current flow to the first inverter circuit (L 41 ) by setting the control signal to be supplied to the control circuit means (SC) to a first state, and limits the current that flows to the first inverter circuit (SC) to a value smaller than the comparatively large current by setting the control signal to be supplied to the control circuit means (SC) to a second state different from the first state. The latch circuits (L 42 , L 43 ) output a signal at a first level or a second level on the basis of a signal outputted by the first inverter circuit (L 41 ) when the control signal is at the first state and outputs the signal at the first level when the control signal is at the second state. COPYRIGHT: (C)2003,JPO

8. 发明专利

JP2003257181A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003257181A
公开(公告)日：2003-09-12
申请号：JP2002058154
申请日：2002-03-05
申请人： HITACHI LTD
发明人： TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , SAKATA TAKESHI
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide constitution of a sense amplifier realizing quick access and a short cycle time when array voltage is made low voltage in a DRAM. SOLUTION: In a TG clocking sense system separating data lines of an array side from data lines of a sense amplifier side at the beginning of sense, a restoring amplifier RAP amplifying a data line of the array side is added referring to data in the sense amplifier is added, and the restoring amplifier is driven by higher voltage VDH than array voltage VDL. Thereby, high speed sense operation of the TG clocking system and high speed restoring operation of an over-drive system can be compatible. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2003045181A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2003045181A
公开(公告)日：2003-02-14
申请号：JP2001228869
申请日：2001-07-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TAKESHI , SEKIGUCHI TOMONORI
IPC分类号： G11C11/407 , G11C11/409 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having small amplitude interface by which high speed and stable operation is performed.
SOLUTION: In an input circuit, an output of a first differential comparator comparing a signal, to which reference signals VTRb and VTRt are divided internally effectively with a desired first ratio, with an input signal D and an output of a second differential comparator comparing a signal, to which reference signals VTRb and VTRt are divided internally effectively with a desired second ratio, with an input signal D are switched by a switching logic circuit STL. Effective signal quantity at the time of transition can be enlarged, securing voltage margin at the time of non-transition of the input signal D.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种具有小幅度接口的半导体器件，通过该接口进行高速和稳定的操作。解决方案：在输入电路中，比较信号的第一差分比较器的输出与参考信号VTRb和VTRt被内部有效地以期望的第一比率分配，输入信号D和第二差分比较器的输出比较信号通过开关逻辑电路STL切换到哪个参考信号VTRb和VTRt以期望的第二比例内部有效地分配，输入信号D被切换。可以扩大转换时的有效信号量，确保输入信号D的非转换时的电压余量。

10. 发明专利

JP2002290225A SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：JP2002290225A
公开(公告)日：2002-10-04
申请号：JP2001393105
申请日：2001-12-26
申请人： HITACHI LTD
发明人： HORIGUCHI SHINJI , ITO KIYOO , SAKATA TAKESHI
IPC分类号： H01L21/822 , G11C11/407 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/00 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit operated at a high-speed with small power consumption. SOLUTION: The threshold voltage of MOS transistors(TRs) MP12 , MP22 , MN12 , MN22 used for latching information is selected higher than the threshold of MOS TRs MP11 , MP21 , MN11 , MN21 to which an input signal is applied. A low threshold voltage is set to a path giving effect on a high-speed operation to attain compatibility between high-speed performance and small power consumption.

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