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1. 发明专利

JP2011013836A Memory arrangement management device and microprocessor 审中-公开
标题翻译：内存安排管理设备和微处理器
公开(公告)号：JP2011013836A
公开(公告)日：2011-01-20
申请号：JP2009156047
申请日：2009-06-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OKAZAKI KEITARO , ASAHI TAKESHI , NAGAI YASUSHI , KAWAHARA TAKAYUKI , MATSUOKA HIDEYUKI , IGUCHI SHINYA , OBINATA NOBUAKI
IPC分类号： G06F9/445 , G06F1/32
摘要： PROBLEM TO BE SOLVED: To solve the following problem of an apparatus including a volatile memory: the apparatus cannot be used during start-up, and even when only scheduled processing is executed after start-up, it is necessary to read all information for start-up.SOLUTION: The memory arrangement management device is provided in an apparatus 103 including a microprocessor 104, a volatile memory 102, a non-volatile memory 108, and a memory arrangement management part 111. The apparatus includes: a first state in which the volatile memory is power off; and a second state in which the volatile memory is power on. The microprocessor has suspension state and operation state, which are selectable. The memory arrangement management device stores, onto the non-volatile memory, information needed when the first state and the operation state are entered before transition to the first state and the suspension state from the second state and the operation state.
摘要翻译：要解决的问题：为了解决包括易失性存储器的装置的以下问题：在启动期间不能使用该装置，并且即使仅在启动之后执行调度处理，则需要读取所有开始的信息解决方案：存储器布置管理装置提供在包括微处理器104，易失性存储器102，非易失性存储器108和存储器布置管理部分111的装置103中。该装置包括：第一状态，其中易失性存储器断电; 以及其中易失性存储器通电的第二状态。微处理器具有可选择的悬架状态和运行状态。存储器配置管理装置在转移到第一状态之前进入第一状态和操作状态所需的信息到非易失性存储器上，并且从第二状态和操作状态存储暂停状态。

2. 发明专利

JP2010108253A Apparatus using nonvolatile memory as main memory 有权
标题翻译：使用非易失性存储器作为主存储的设备
公开(公告)号：JP2010108253A
公开(公告)日：2010-05-13
申请号：JP2008279770
申请日：2008-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IGUCHI SHINYA , NAGAI YASUSHI , OKAZAKI KEITARO , ASAHI TAKESHI , KAWAHARA TAKAYUKI , MATSUOKA HIDEYUKI
IPC分类号： G06F12/16 , G06F1/30
摘要： PROBLEM TO BE SOLVED: To solve the problem that a system can not normally resume operation when power supply is suddenly interrupted, and then is powered on again in the case where a main memory is composed of a nonvolatile memory as a whole. SOLUTION: The apparatus comprises an abnormal power supply cutoff determination section and an abnormal power supply end notification register. When the apparatus is powered on, the abnormal power supply cutoff determination section refers to the abnormal power supply end notification register and in the case where the abnormal power supply end notification register stores beforehand information indicating that power supply to the apparatus is abnormally cut off and where a processor is not a nonvolatile processor, the abnormal power supply cutoff determination section re-initiates a process being executed prior to cutting off power supply to the apparatus and confirms a device driver. In the case where the abnormal power supply end notification register stores beforehand information indicating that power supply to the apparatus is abnormally cut off and that the processor is a nonvolatile processor, the abnormal power supply cutoff determination section resumes the process being executed prior to cutting off power supply to the apparatus from processing, in which the process is interrupted, and confirms the device driver. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了解决在电源突然中断时系统无法正常恢复运行的问题，并且在主存储器整体由非易失性存储器组成的情况下再次通电的问题。解决方案：该装置包括异常电源切断判定部和异常供电结束通知寄存器。当设备通电时，异常电源切断判断部分参考异常供电结束通知寄存器，并且在异常供电结束通知寄存器预先存储指示对设备的电力供应被异常切断的信息，以及在处理器不是非易失性处理器的情况下，异常电源切断判定部在切断对该装置的电力供给之前，重新启动正在执行的处理，并确认设备驱动器。在异常供电结束通知寄存器预先存储表示设备的电源被异常切断并且处理器是非易失性处理器的信息的情况下，异常电源切断判断部件在切断之前恢复正在执行的处理从处理中向设备供电，其中处理中断，并确认设备驱动程序。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2007250185A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007250185A
公开(公告)日：2007-09-27
申请号：JP2007179193
申请日：2007-07-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HANZAWA SATORU , SAKATA TAKESHI , MATSUOKA HIDEYUKI
IPC分类号： G11C11/15
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of realizing a large capacity magneto-resistive random access memory (MRAM) having higher integration and higher reliability. SOLUTION: The device is provided with a plurality of first memory cells MC arranged at intersections of plurality of word lines WE0 to WR7and a plurality of first data lines D0 to D7 and storing either of "1" or "0", a plurality of first dummy cells MCH arranged at intersections of a plurality of word lines WR0 to WR7 and a first dummy data line DD0 and storing "1", and a plurality of second dummy cells MCL arranged at intersections of a plurality of word lines WR0 to WR7 and a second dummy data line DD1 and storing "0". Writing information in the first and the second dummy cells is performed using a writing circuit in the same way as the plurality of memory cells. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供能够实现具有更高集成度和更高可靠性的大容量磁阻随机存取存储器（MRAM）的半导体器件。解决方案：该装置设置有多个第一存储单元MC，其布置在多个字线WE0至WR7和多个第一数据线D0至D7的交点处，并存储“1”或“0”之一，多个第一虚拟单元MCH，其布置在多个字线WR0至WR7和第一虚拟数据线DD0的交点处并存储“1”，以及多个第二虚拟单元MCL，布置在多个字线WR0至 WR7和第二伪数据线DD1，并存储“0”。以与多个存储单元相同的方式，使用写入电路来执行第一和第二虚拟单元中的写入信息。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2004349504A Semiconductor integrated circuit device 有权
公开(公告)号：JP2004349504A
公开(公告)日：2004-12-09
申请号：JP2003145305
申请日：2003-05-22
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKAURA NORIKATSU , MATSUOKA HIDEYUKI , TERAO MOTOYASU , KUROTSUCHI KENZO , YAMAUCHI TAKESHI
IPC分类号： H01L27/10 , H01L27/105 , H01L27/115 , H01L27/24 , H01L29/02
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： PROBLEM TO BE SOLVED: To improve on the reliability of the rewrite frequency of a high-speed nonvolatile phase change memory device.
SOLUTION: In the memory cell forming region for a phase change memory wherein a MISFET is used as a memory cell selecting transistor QM, a phase change material layer CG is common to the memory cells comprising resistance elements R using the phase change material. Geometrical variation and change in the phase change material composition otherwise to occur due to memory cell element separation during the dry etching process are reduced for the improvement of reliability in memory cell rewrite frequency.
COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2004086986A Semiconductor device 有权
公开(公告)号：JP2004086986A
公开(公告)日：2004-03-18
申请号：JP2002246092
申请日：2002-08-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TAKESHI , MATSUOKA HIDEYUKI
IPC分类号： G11C13/00 , G11C7/10 , G11C11/15 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
CPC分类号： G11C7/1096 , G11C7/1006 , G11C7/1078 , G11C11/1673 , G11C11/1675
摘要： PROBLEM TO BE SOLVED: To provide a highly integrated high-speed nonvolatile memory of small power consumption and low power in writing. SOLUTION: Compared with read data GO read out by a data encoder WC from a memory cell array in write operation, input data DI are encoded to be data GI, and the read data GO are decoded by a data decoder RD to be output data DO. In a nonvolatile semiconductor memory for writing data into a memory cell by flowing current through a data line, power consumption can be reduced by reducing the number of bits for writing in the write operation. Thus, an MRAM having a highly integrated memory with low power consumption can be realized. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2003224211A SEMICONDUCTOR MEMORY 审中-公开
公开(公告)号：JP2003224211A
公开(公告)日：2003-08-08
申请号：JP2002360105
申请日：2002-12-12
申请人： HITACHI LTD
发明人： TAKAURA NORIKATSU , MATSUOKA HIDEYUKI , TAKEMURA RIICHIRO , OKUYAMA KOSUKE , SHIGENIWA MASAHIRO , NISHIDA AKIO , FUNAYAMA KOTA , SEKIGUCHI TOMONORI
IPC分类号： G11C11/41 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/10
摘要： PROBLEM TO BE SOLVED: To provide a miniature and small power SRAM cell for use in an SRAM device, and a 64 Mbit or 128 Mbit ultra-small power SRAM and high density cache SRAM for a portable telephone. SOLUTION: The semiconductor memory device comprises a plurality of electrostatic memory cells having a plurality of word lines and bit lines and first through sixth transistors, respectively. Channels of first through fourth transistors are formed perpendicular to the substrate of the semiconductor memory device and the semiconductor regions forming the sources or drains of the fifth and sixth transistors form a PN junction with respect to the substrate. COPYRIGHT: (C)2003,JPO

7. 发明专利

JP2003193866A GAS TURBINE COMBUSTOR 审中-公开
公开(公告)号：JP2003193866A
公开(公告)日：2003-07-09
申请号：JP2001391064
申请日：2001-12-25
申请人： HITACHI LTD , CHUBU ELECTRIC POWER
发明人： ARIKAWA HIDEYUKI , ICHIKAWA KUNIHIRO , SUGITA YUJI , SHINOHARA NOBUO , MATSUOKA HIDEYUKI
IPC分类号： F02C7/28 , C22C19/07 , C23C16/40 , F23R3/42
摘要： PROBLEM TO BE SOLVED: To provide a gas turbine combustor having a wear resistant structure to prevent wear and damage occurring in a fitting part of a frame part of a combustor transition piece and a seal material during gas turbine operation. SOLUTION: In this gas turbine combustor, the fitting part of the transition piece is constituted by forming an alumina film having a film of carbide or nitride as a substrate on a surface of the seal material using a cobalt-based alloy containing 0.2 wt.% or less carbon as the seal material and having a thickness of 0.5 to 6 μm and attaching a plate member (protection plate) made of the cobalt-based alloy containing 15 to 35 wt.% chromium and 0.7 to 1.5 wt.% carbon to a contact part of the seal materials 3, 4 in the frame part 2 of the transition piece 1 on a mate side. COPYRIGHT: (C)2003,JPO

8. 发明专利

JP2002367365A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2002367365A
公开(公告)日：2002-12-20
申请号：JP2001176465
申请日：2001-06-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TAKESHI , HANZAWA SATORU , MATSUOKA HIDEYUKI , WATANABE KATSURO , ITOU AKITOMO
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08
CPC分类号： H01L27/226 , B82Y10/00 , G11C11/16
摘要： PROBLEM TO BE SOLVED: To make read-out operation high S/N in an MRAM using a memory cell storing information utilizing variation of magnetic resistance of an MTJ element. SOLUTION: A memory cell is constituted by comprising an MTJ element and a bipolar transistor QMC. Read-out operation is performed by current- amplifying a current IWL flowing the MTJ element by the bipolar transistor by selecting a word line WL and outputting it to a read-out data line DR. Thereby, high S/N read-out operation can be performed, a semiconductor device having an MRAM having high speed, high integration, and high reliability.
摘要翻译：要解决的问题：使用存储使用MTJ元件的磁阻的变化的信息的存储单元，使MRAM中的读出操作高S / N。解决方案：存储单元由MTJ元件和双极晶体管QMC构成。通过选择字线WL并将其输出到读出数据线DR来电流放大由双极型晶体管流过MTJ元件的电流IWL来执行读出操作。因此，可以执行高S / N读出操作，具有高速度，高集成度和高可靠性的MRAM的半导体器件。

9. 发明专利

JP2002222589A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2002222589A
公开(公告)日：2002-08-09
申请号：JP2001341365
申请日：2001-11-07
申请人： HITACHI LTD
发明人： HANZAWA SATORU , SAKATA TAKESHI , MATSUOKA HIDEYUKI
IPC分类号： G11C11/14 , G11C11/15 , G11C29/00 , G11C29/04
摘要： PROBLEM TO BE SOLVED: To provide a reference signal generating method used for read-out operation of a memory cell for storing information by utilizing the variation of magnetic resistance, and to provide a dummy cell. SOLUTION: The dummy cell is provided with plural first memory cells MC arranged at intersections of plural word lines WR0-WR7 and plural first data lines D0-D7 and storing either of '1' or '1', plural first dummy cells MCH arranged at intersections of plural work line WR0-WR7 and a first dummy data line DD0 and storing '1', and plural second dummy cells MCL arranged at intersections opf plural word lines WR0-WR7 and a second dummy data line DD1 and storing '0'. Therefore, a MRAM having higher integration, higher reliability, and larger capacity than heretofore can be realized.

10. 发明专利

JPH1079478A DYNAMIC RAM DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1079478A
公开(公告)日：1998-03-24
申请号：JP23427296
申请日：1996-09-04
申请人： HITACHI LTD
发明人： YAMANAKA TOSHIAKI , KIMURA SHINICHIRO , ITO KIYOO , MATSUOKA HIDEYUKI , SEKIGUCHI TOMONORI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve resistance with respect to soft error and reliability by increasing the depth of a trench of a solid capacitor for charge storage, formed at a position higher than a substrate upper surface. SOLUTION: A switch transistor is an n-channel type MISFET formed in a region on a p-type silicon substrate 1 isolated with a field oxide film 2, and a gate electrode 4 is a word line on an active region. A wiring electrode 8 is a data line connected to a high-concentration n-type impurity region 5 of a source (or drain) of the switch transistor. Further, a storage electrode 12 of the capacitor for charge storage is provided at the upper ends of the word line and the data line. The storage electrode 12 is connected to a high- concentration n-type impurity region 6 of the MISFET in the memory cell via a silicon plug 10. The storage electrode 12, formed in a trench shape, includes a rectangular-parallelepiped plate electrode 14 via a capacitor insulating film 13 which is between the inner wall of the electrode 12 and the plate electrode 14.

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