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1. 发明专利

JP2011013836A Memory arrangement management device and microprocessor 审中-公开
标题翻译：内存安排管理设备和微处理器
公开(公告)号：JP2011013836A
公开(公告)日：2011-01-20
申请号：JP2009156047
申请日：2009-06-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OKAZAKI KEITARO , ASAHI TAKESHI , NAGAI YASUSHI , KAWAHARA TAKAYUKI , MATSUOKA HIDEYUKI , IGUCHI SHINYA , OBINATA NOBUAKI
IPC分类号： G06F9/445 , G06F1/32
摘要： PROBLEM TO BE SOLVED: To solve the following problem of an apparatus including a volatile memory: the apparatus cannot be used during start-up, and even when only scheduled processing is executed after start-up, it is necessary to read all information for start-up.SOLUTION: The memory arrangement management device is provided in an apparatus 103 including a microprocessor 104, a volatile memory 102, a non-volatile memory 108, and a memory arrangement management part 111. The apparatus includes: a first state in which the volatile memory is power off; and a second state in which the volatile memory is power on. The microprocessor has suspension state and operation state, which are selectable. The memory arrangement management device stores, onto the non-volatile memory, information needed when the first state and the operation state are entered before transition to the first state and the suspension state from the second state and the operation state.
摘要翻译：要解决的问题：为了解决包括易失性存储器的装置的以下问题：在启动期间不能使用该装置，并且即使仅在启动之后执行调度处理，则需要读取所有开始的信息解决方案：存储器布置管理装置提供在包括微处理器104，易失性存储器102，非易失性存储器108和存储器布置管理部分111的装置103中。该装置包括：第一状态，其中易失性存储器断电; 以及其中易失性存储器通电的第二状态。微处理器具有可选择的悬架状态和运行状态。存储器配置管理装置在转移到第一状态之前进入第一状态和操作状态所需的信息到非易失性存储器上，并且从第二状态和操作状态存储暂停状态。

2. 发明专利

JP2010108253A Apparatus using nonvolatile memory as main memory 有权
标题翻译：使用非易失性存储器作为主存储的设备
公开(公告)号：JP2010108253A
公开(公告)日：2010-05-13
申请号：JP2008279770
申请日：2008-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IGUCHI SHINYA , NAGAI YASUSHI , OKAZAKI KEITARO , ASAHI TAKESHI , KAWAHARA TAKAYUKI , MATSUOKA HIDEYUKI
IPC分类号： G06F12/16 , G06F1/30
摘要： PROBLEM TO BE SOLVED: To solve the problem that a system can not normally resume operation when power supply is suddenly interrupted, and then is powered on again in the case where a main memory is composed of a nonvolatile memory as a whole. SOLUTION: The apparatus comprises an abnormal power supply cutoff determination section and an abnormal power supply end notification register. When the apparatus is powered on, the abnormal power supply cutoff determination section refers to the abnormal power supply end notification register and in the case where the abnormal power supply end notification register stores beforehand information indicating that power supply to the apparatus is abnormally cut off and where a processor is not a nonvolatile processor, the abnormal power supply cutoff determination section re-initiates a process being executed prior to cutting off power supply to the apparatus and confirms a device driver. In the case where the abnormal power supply end notification register stores beforehand information indicating that power supply to the apparatus is abnormally cut off and that the processor is a nonvolatile processor, the abnormal power supply cutoff determination section resumes the process being executed prior to cutting off power supply to the apparatus from processing, in which the process is interrupted, and confirms the device driver. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了解决在电源突然中断时系统无法正常恢复运行的问题，并且在主存储器整体由非易失性存储器组成的情况下再次通电的问题。解决方案：该装置包括异常电源切断判定部和异常供电结束通知寄存器。当设备通电时，异常电源切断判断部分参考异常供电结束通知寄存器，并且在异常供电结束通知寄存器预先存储指示对设备的电力供应被异常切断的信息，以及在处理器不是非易失性处理器的情况下，异常电源切断判定部在切断对该装置的电力供给之前，重新启动正在执行的处理，并确认设备驱动器。在异常供电结束通知寄存器预先存储表示设备的电源被异常切断并且处理器是非易失性处理器的信息的情况下，异常电源切断判断部件在切断之前恢复正在执行的处理从处理中向设备供电，其中处理中断，并确认设备驱动程序。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2007250185A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007250185A
公开(公告)日：2007-09-27
申请号：JP2007179193
申请日：2007-07-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HANZAWA SATORU , SAKATA TAKESHI , MATSUOKA HIDEYUKI
IPC分类号： G11C11/15
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of realizing a large capacity magneto-resistive random access memory (MRAM) having higher integration and higher reliability. SOLUTION: The device is provided with a plurality of first memory cells MC arranged at intersections of plurality of word lines WE0 to WR7and a plurality of first data lines D0 to D7 and storing either of "1" or "0", a plurality of first dummy cells MCH arranged at intersections of a plurality of word lines WR0 to WR7 and a first dummy data line DD0 and storing "1", and a plurality of second dummy cells MCL arranged at intersections of a plurality of word lines WR0 to WR7 and a second dummy data line DD1 and storing "0". Writing information in the first and the second dummy cells is performed using a writing circuit in the same way as the plurality of memory cells. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供能够实现具有更高集成度和更高可靠性的大容量磁阻随机存取存储器（MRAM）的半导体器件。解决方案：该装置设置有多个第一存储单元MC，其布置在多个字线WE0至WR7和多个第一数据线D0至D7的交点处，并存储“1”或“0”之一，多个第一虚拟单元MCH，其布置在多个字线WR0至WR7和第一虚拟数据线DD0的交点处并存储“1”，以及多个第二虚拟单元MCL，布置在多个字线WR0至 WR7和第二伪数据线DD1，并存储“0”。以与多个存储单元相同的方式，使用写入电路来执行第一和第二虚拟单元中的写入信息。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2004349504A Semiconductor integrated circuit device 有权
公开(公告)号：JP2004349504A
公开(公告)日：2004-12-09
申请号：JP2003145305
申请日：2003-05-22
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKAURA NORIKATSU , MATSUOKA HIDEYUKI , TERAO MOTOYASU , KUROTSUCHI KENZO , YAMAUCHI TAKESHI
IPC分类号： H01L27/10 , H01L27/105 , H01L27/115 , H01L27/24 , H01L29/02
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： PROBLEM TO BE SOLVED: To improve on the reliability of the rewrite frequency of a high-speed nonvolatile phase change memory device.
SOLUTION: In the memory cell forming region for a phase change memory wherein a MISFET is used as a memory cell selecting transistor QM, a phase change material layer CG is common to the memory cells comprising resistance elements R using the phase change material. Geometrical variation and change in the phase change material composition otherwise to occur due to memory cell element separation during the dry etching process are reduced for the improvement of reliability in memory cell rewrite frequency.
COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2004086986A Semiconductor device 有权
公开(公告)号：JP2004086986A
公开(公告)日：2004-03-18
申请号：JP2002246092
申请日：2002-08-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TAKESHI , MATSUOKA HIDEYUKI
IPC分类号： G11C13/00 , G11C7/10 , G11C11/15 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
CPC分类号： G11C7/1096 , G11C7/1006 , G11C7/1078 , G11C11/1673 , G11C11/1675
摘要： PROBLEM TO BE SOLVED: To provide a highly integrated high-speed nonvolatile memory of small power consumption and low power in writing. SOLUTION: Compared with read data GO read out by a data encoder WC from a memory cell array in write operation, input data DI are encoded to be data GI, and the read data GO are decoded by a data decoder RD to be output data DO. In a nonvolatile semiconductor memory for writing data into a memory cell by flowing current through a data line, power consumption can be reduced by reducing the number of bits for writing in the write operation. Thus, an MRAM having a highly integrated memory with low power consumption can be realized. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2002367365A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2002367365A
公开(公告)日：2002-12-20
申请号：JP2001176465
申请日：2001-06-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TAKESHI , HANZAWA SATORU , MATSUOKA HIDEYUKI , WATANABE KATSURO , ITOU AKITOMO
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L43/08
CPC分类号： H01L27/226 , B82Y10/00 , G11C11/16
摘要： PROBLEM TO BE SOLVED: To make read-out operation high S/N in an MRAM using a memory cell storing information utilizing variation of magnetic resistance of an MTJ element. SOLUTION: A memory cell is constituted by comprising an MTJ element and a bipolar transistor QMC. Read-out operation is performed by current- amplifying a current IWL flowing the MTJ element by the bipolar transistor by selecting a word line WL and outputting it to a read-out data line DR. Thereby, high S/N read-out operation can be performed, a semiconductor device having an MRAM having high speed, high integration, and high reliability.
摘要翻译：要解决的问题：使用存储使用MTJ元件的磁阻的变化的信息的存储单元，使MRAM中的读出操作高S / N。解决方案：存储单元由MTJ元件和双极晶体管QMC构成。通过选择字线WL并将其输出到读出数据线DR来电流放大由双极型晶体管流过MTJ元件的电流IWL来执行读出操作。因此，可以执行高S / N读出操作，具有高速度，高集成度和高可靠性的MRAM的半导体器件。

7. 发明专利

JP2005116923A Nonvolatile magnetic memory cell using spin torque and magnetic random access memory using same 审中-公开
标题翻译：使用旋转扭矩和磁性随机存取存储器的非易失性磁记忆单元
公开(公告)号：JP2005116923A
公开(公告)日：2005-04-28
申请号：JP2003351788
申请日：2003-10-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAYAKAWA JUN , MATSUOKA HIDEYUKI
IPC分类号： G11C11/15 , G11C11/14 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： PROBLEM TO BE SOLVED: To provide a high integration memory cell which has a function of reversing spin-torque magnetization and has super-low power consumption in a nonvolatile magnetic memory, and also to provide a random access memory using the memory cell.
SOLUTION: The memory cell comprises a spin-torque magnetization reversal layer and a tunnel magnetoresistance effect film on a C-MOSFET.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高集成度存储单元，其具有使自旋转矩磁化反转的功能，并且在非易失性磁存储器中具有超低功耗，并且还提供使用该存储单元的随机存取存储器。解决方案：存储单元包括C-MOSFET上的自旋扭矩磁化反转层和隧道磁阻效应膜。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2003031684A Semiconductor integrated circuit device and its manufacturing method 审中-公开
标题翻译：半导体集成电路设备及其制造方法
公开(公告)号：JP2003031684A
公开(公告)日：2003-01-31
申请号：JP2001211259
申请日：2001-07-11
申请人： Hitachi Ltd , Nec Corp , 日本電気株式会社 , 株式会社日立製作所
发明人： TAKAURA NORIKATSU , MATSUOKA HIDEYUKI , KIMURA SHINICHIRO , NAGAI AKIRA , YAMADA SATORU
IPC分类号： H01L27/108 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L29/49
CPC分类号： H01L27/10894 , H01L21/76895 , H01L21/76897 , H01L21/823857 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L29/4941 , H01L29/6656
摘要： PROBLEM TO BE SOLVED: To improve refresh characteristic of a DRAM memory cell and driving capability of a MISFET which is formed around the memory cell and constitutes a logic circuit. SOLUTION: A gate electrode 5g of a memory cell region is formed by using p-type polycrystalline silicon. A cap insulating film 6 on the gate electrode 5g and a side wall film 7 on the side wall of the gate electrode 5g are made of silicon oxide films. By polishing the polycrystalline silicon on the gate electrodes 5g and a part between the gate electrodes 5g by using a CMP method, contact electrodes 12a, 12b are formed. A side wall film composed of a lamination film of a silicon oxide film 7 and a polycrystalline silicon film is formed on side walls of gate electrodes 8f, 9f of a logic circuit region. By using the films as masks, semiconductor regions 8e, 9e are formed. As the result, boron punch through can be reduced, and the contact electrodes can be formed in a self alignment manner. The driving capability of the MISFET constituting the logic circuit can be improved.
摘要翻译：要解决的问题：提高DRAM存储单元的刷新特性和形成在存储单元周围的MISFET的驱动能力，构成逻辑电路。解决方案：使用p型多晶硅形成存储单元区域的栅电极5g。栅电极5g上的帽绝缘膜6和栅电极5g的侧壁上的侧壁膜7由氧化硅膜构成。通过使用CMP方法研磨栅电极5g上的多晶硅和栅电极5g之间的部分，形成接触电极12a，12b。在逻辑电路区域的栅电极8f，9f的侧壁上形成由氧化硅膜7和多晶硅膜的叠层膜构成的侧壁膜。通过使用膜作为掩模，形成半导体区域8e，9e。结果，可以减少硼穿通，并且可以以自对准方式形成接触电极。可以提高构成逻辑电路的MISFET的驱动能力。

9. 发明专利

JP2009267219A Semiconductor memory device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2009267219A
公开(公告)日：2009-11-12
申请号：JP2008117055
申请日：2008-04-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SASAKO YOSHITAKA , TAKEMURA RIICHIRO , KINOSHITA KATSUJI , MINE TOSHIYUKI , SHIMA AKIO , MATSUOKA HIDEYUKI , HATANO MUTSUKO , TAKAURA NORIKATSU
IPC分类号： H01L27/105 , H01L21/20 , H01L21/265 , H01L27/10 , H01L45/00
CPC分类号： H01L27/2481 , H01L21/02532 , H01L21/02675 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： PROBLEM TO BE SOLVED: To promote large capacity, high performance and high reliability of a semiconductor memory device, by attaining high-performance of both a semiconductor device and a memory element, when the semiconductor memory device is manufactured by stacking a memory element, such as, ReRAM or a phase change memory and the semiconductor device. SOLUTION: After a polysilicon forming a selection element is deposited in an amorphous state at a low temperature, crystallization and activation of impurities are performed with heat treatment, in a short time, by laser annealing. When laser annealing is performed, a recording material which is located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase, at annealing and is able to reduce the thermal load on the recording material. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了通过实现半导体器件和存储元件两者的高性能来提高半导体存储器件的大容量，高性能和高可靠性，当半导体存储器件通过堆叠存储器制造时元件，例如ReRAM或相变存储器和半导体器件。解决方案：在低温下以非晶态沉积形成选择元素的多晶硅后，通过激光退火在短时间内进行热处理来进行杂质的结晶和活化。当进行激光退火时，位于被结晶的硅下方的记录材料被金属膜或金属膜和绝缘膜完全覆盖，从而可以在退火时抑制温度升高，并且是能够降低记录材料的热负荷。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2008217975A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008217975A
公开(公告)日：2008-09-18
申请号：JP2008089124
申请日：2008-03-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TAKESHI , MATSUOKA HIDEYUKI
IPC分类号： G11C11/15 , G11C13/00 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L45/00
摘要： PROBLEM TO BE SOLVED: To solve a problem that current consumption of write operation of a phase change memory is large in order to flow a current required for phase change to a data line. SOLUTION: A semiconductor device has a memory array containing a plurality of memory cells arranged at a desired intersection point of a plurality of word lines and a plurality of data lines and a write buffer which drives both ends of the data line and flows a write current. Each of the plurality of memory cells includes a phase transition resistance element and a transistor. The write-buffer drives the data line only when performing reverse write to the memory cell of the data line. In a nonvolatile semiconductor memory in which data is written in the memory cell by flowing the current to the data line, current consumption can be reduced by reducing the number of bits which performs write in write operation. Thereby the phase change memory having a memory of high integration can be achieved with low power. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决相变存储器的写入操作的电流消耗大以使相变所需的电流流向数据线的问题。解决方案：半导体器件具有存储器阵列，该存储器阵列包含布置在多个字线和多条数据线的期望交点处的多个存储单元，以及驱动数据线的两端并流动的写入缓冲器写入电流。多个存储单元中的每一个包括相变电阻元件和晶体管。只有在对数据线的存储单元进行反向写操作时，写缓冲区才会驱动数据线。在通过使电流流向数据线而将数据写入存储单元的非易失性半导体存储器中，通过减少在写入操作中执行写入的位数，可以减少电流消耗。由此，能够以低功率实现具有高集成度的存储器的相变存储器。版权所有（C）2008，JPO＆INPIT

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