专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2002368126A Production method for semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备的生产方法
公开(公告)号：JP2002368126A
公开(公告)日：2002-12-20
申请号：JP2001176472
申请日：2001-06-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMANAKA TOSHIAKI , NISHIDA AKIO , YOSHIDA YASUKO , IKEDA SHUJI , KURODA KENICHI , KANBARA SHIRO , KIMURA SHINICHIRO , MURAKAMI HIDEKAZU , MATSUOKA HIDEYUKI , MINAMI MASATAKA
IPC分类号： H01L27/092 , H01L21/265 , H01L21/266 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/2652 , H01L21/823842 , H01L21/823892
摘要： PROBLEM TO BE SOLVED: To solve the problem of production costs increasing due to increased production processes, since photomasks are required as many as the number of kinds of wells, channels stoppers, gate electrodes and ion implantations for threshold control or the like.
SOLUTION: Areas for NMIS of a low Vth and PMIS of a high Vth are set, by using a photoresist mask for forming the well as well, and the regions for the NMIS of high Vth and the PMIS of low Vth are set through one ion implantation process by the photoresist mask of a opening part common to the NMIS and the PMIS. Also, after oxidizing of the gate, ion implantation to the well, channel and the gate electrode are performed through a noncrystalline silicon film. Therefore, setting of the threshold voltage for a plurality of CMIS or gate electrodes of both polarities can be provided by fewer photoresist processes.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了解决由于生产工艺的增加而导致的生产成本增加的问题，由于光掩模需要孔数，通道挡块，栅电极和用于阈值控制的离子注入等的数量。解决方案：通过使用用于形成阱的光致抗蚀剂掩模来设置具有高Vth的低Vth和PMIS的NMIS的区域，并且通过一个离子设置高Vth的NMIS的区域和低Vth的NMIS的区域通过NMIS和PMIS共同的开口部分的光刻胶掩模进行注入工艺。此外，在栅极氧化之后，通过非晶硅膜进行到阱，沟道和栅电极的离子注入。因此，可以通过较少的光刻胶工艺来提供两个极性的多个CMIS或栅电极的阈值电压的设置。

2. 发明专利

JP2002368056A Method for providing yield conditions, method for determining production conditions, method for fabricating semiconductor device and recording medium 审中-公开
标题翻译：用于提供线条条件的方法，用于确定生产条件的方法，用于制造半导体器件和记录介质的方法
公开(公告)号：JP2002368056A
公开(公告)日：2002-12-20
申请号：JP2001171572
申请日：2001-06-06
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWAKAMI MEGUMI , KANBARA SHIRO , SENTODA TAKESHI , MIYAMA MIKAKO
IPC分类号： H01L21/66 , H01L21/00
摘要： PROBLEM TO BE SOLVED: To analyze the factor for enhancing the yield with high precision in a short term.
SOLUTION: Data of wafer inspection and probe inspection is pigeonholed and abnormal values are deleted (steps S101-S103), probe inspection terms are predicted (step S105) from the results of data mining (step S104), and the yield is predicted (step S106) from the results of the steps S103 and S105. A decision is then made whether correlation is present between the predicted value of yield and an actually measured value (steps S107, S108) and optimal conditions are determined from the order of influence of the yield (step S109). Trial manufacturing is performed for recognition if the conditions satisfy a target spectfication, otherwise splitting is performed for each category according to an orthogonal table (step S201), a semiconductor wafer is produced by way of trial according to trial production conditions thus obtained and abnormal values are deleted from probe inspection data (steps S202-S204), and then the conditions are optimized by analyzing the causes (steps S205, S206).
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：在短期内以高精度分析提高产量的因素。解决方案：从数据挖掘的结果（步骤S104），晶片检查和探针检查的数据被排除并且异常值被删除（步骤S101-S103），探测检查项（步骤S105），并且预测产量（步骤 S106）的步骤S103和S105的结果。然后，判定在预测的收益值与实际测量值之间是否存在相关性（步骤S107，S108），并根据收益的影响顺序确定最优条件（步骤S109）。如果条件满足目标观察，则执行用于识别的试生产，否则根据正交表对每个类别进行分割（步骤S201），根据如此获得的试生产条件通过试验生产半导体晶片和异常值（步骤S202〜S204），然后通过分析原因优化条件（步骤S205，S206）。

3. 发明专利

JP2003031680A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003031680A
公开(公告)日：2003-01-31
申请号：JP2001214811
申请日：2001-07-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKAI KENJI , SHIBA KAZUYOSHI , KANBARA SHIRO , NAKAJIMA NOBUE , KURODA KENICHI
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66575 , H01L21/823807 , H01L21/823857 , H01L21/823892
摘要： PROBLEM TO BE SOLVED: To improve electrical characteristics of a field effect transistor. SOLUTION: The method for manufacturing a semiconductor device comprises the steps of forming a gate insulating film 3 and a gate electrode 4a on a semiconductor substrate 1S, and then implanting an impurity to form a channel region 6 of the field effect transistor.
摘要翻译：要解决的问题：改善场效应晶体管的电气特性。解决方案：半导体器件的制造方法包括以下步骤：在半导体衬底1S上形成栅绝缘膜3和栅电极4a，然后注入杂质以形成场效应晶体管的沟道区6。

4. 发明专利

JP2004096119A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004096119A
公开(公告)日：2004-03-25
申请号：JP2003320604
申请日：2003-09-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOSHINO YUTAKA , IKEDA SHUJI , YOSHIDA ISAO , KANBARA SHIRO , KAWAKAMI MEGUMI , MIYAKE TOMOYUKI , MORIKAWA MASATOSHI
IPC分类号： H01L29/41 , H01L21/768 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/78
CPC分类号： H01L29/41758 , H01L29/4175 , H01L29/7835 , H01L2224/49175 , H01L2924/13091 , H01L2924/19105 , H01L2924/3011 , H01L2924/30111 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To make fine a MOSFET for high frequency amplification having a drain offsetting region and, at the same time, lower its on-resistance. SOLUTION: In the MOSFET, electrode leading-out conductor plugs 13(p1) are respectively provided on a source region 10, a drain region 9, and a reach-through layer 3(4). Two layers of first-layer wiring 11s and 11d(M1) are respectively connected to the plugs 13(p1), and two layers of second-layer wiring 12s and 12d for back lining are respectively connected to the first-layer wiring 11s and 11d(M1) on the plugs 13(p1). COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2004096118A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004096118A
公开(公告)日：2004-03-25
申请号：JP2003320603
申请日：2003-09-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOSHINO YUTAKA , IKEDA SHUJI , YOSHIDA ISAO , KANBARA SHIRO , KAWAKAMI MEGUMI , MIYAKE TOMOYUKI , MORIKAWA MASATOSHI
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/4175 , H01L29/41758 , H01L2224/48227 , H01L2224/49111 , H01L2224/49175 , H01L2924/13091 , H01L2924/19105 , H01L2924/3011 , H01L2924/30111 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To make fine a MOSFET for high frequency amplification having a drain offsetting region fine and, at the same time, lower its on-resistance. SOLUTION: In the MOSFET, electrode leading-out conductor plugs 13(p1) are respectively provided on a source region 10, a drain region 9, and a reach-through layer 3 (4). Two layers of first-layer wiring 11s and 11d(M1) are respectively connected to the conductor plugs 13(p1), and two layers of second-layer wiring 12s and 12d for back lining are respectively connected to the first-layer wiring 11s and 11d(M1) on the plugs 13(p1). COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了使具有漏极偏移区域的高频放大的MOSFET精细化，并且同时降低其导通电阻。解决方案：在MOSFET中，电极引出导体插头13（p1）分别设置在源极区域10，漏极区域9和贯通层3（4）上。两层第一层布线11s和11d（M1）分别连接到导体插头13（p1），两层用于背衬的第二层布线12s和12d分别连接到第一层布线11s和 11d（M1）在插头13（p1）上。版权所有（C）2004，JPO

6. 发明专利

JP2002353083A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002353083A
公开(公告)日：2002-12-06
申请号：JP2001153469
申请日：2001-05-23
申请人： HITACHI LTD
发明人： MIYAMA MIKAKO , KANBARA SHIRO , OJI YUZURU , OKUYAMA KOSUKE , KAWAKAMI MEGUMI
IPC分类号： G06F17/50 , H01L21/02
摘要： PROBLEM TO BE SOLVED: To materialize the rise of the manufacture efficiency of an LSI or the reduction of manufacture cost, by integrating and utilizing the information about both design division and a manufacture division. SOLUTION: A computer unit (60) receives the input of the element property information of a semiconductor element from manufacture divisions (10-12) and also receives the input of design information of a semiconductor integrated circuit from manufacturing divisions (13-16) via a network, and creates the response information requested by a request source concerned, based on the above input information, in response to the request from the supply source of the above design information, and returns the created response information to the above request source. For example, the response information is the forecast yield information, at the time of having supposed that the semiconductor integrated circuit is constituted, making use of the element specified by the element property information. Hereby, the design division can be previously informed of the yield of products at the time of having placed an order with the manufacture division with products, and it becomes possible to properly select the manufacture division. The enhancement of the manufacture efficiency of LSI or the reduction of manufacture cost can be materialized by using the properly selected manufacture division.

7. 发明专利

JP2002151599A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2002151599A
公开(公告)日：2002-05-24
申请号：JP2000344691
申请日：2000-11-13
申请人： HITACHI LTD
发明人： MATSUURA TATSUJI , KUBO SEIJI , HOTTA MASAO , KANBARA SHIRO , NAKAJIMA NOBUE
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve noise characteristics of a semiconductor integrated circuit device with an analog/digital coexisting. SOLUTION: The gate insulation film 3 of MSI.FETQ constituting the analog circuit of the analog/digital coexisting circuit is constituted of an acid nitride film and at least one MIS.FETQ constituting the analog circuit is turned to a structure provided with a depression type buried channel layer 5b.

8. 发明专利

JP2002110944A SEMICONDUCTOR STORAGE DEVICE, ITS EVALUATION METHOD AND METHOD FOR DEVELOPING SEMICONDUCTOR STORAGE DEVICE USING THE EVALUATION METHOD 失效
公开(公告)号：JP2002110944A
公开(公告)日：2002-04-12
申请号：JP2000295614
申请日：2000-09-28
申请人： HITACHI LTD
发明人： MORI TOMONORI , KANBARA SHIRO , SHIGENIWA MASAHIRO , OYU SHIZUNORI , OKUYAMA KOSUKE , YAMADA RENICHI , YAMANAKA TOSHIAKI
IPC分类号： G01R31/28 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a memory cell evaluation method which predicts and evaluates data-holding characteristic of a semiconductor memory by using a semiconductor device for estimation (TEG), without having to conduct refresh test accompanied by circuit operation. SOLUTION: A corresponding relation is held between distribution (a) of data-holding characteristic and distribution (b) of a TEG leakage current, which is obtained by measurement of TEG wherein a plurality of memory cell transistors are connected in parallel. Since normal distribution and tail distribution of a TEG leakage current are determined by normal distribution and tail distribution of data-holding characteristic, prediction is made possible by using TEG measurement. By obtaining a relation suitable for estimating data-holding characteristic between the number of memory cell transistors which are contained in the TEG and connected in parallel and the number of measurements of the TEG, a TEG leakage current is measured in a range of the number condition, and data-holding characteristic is predicted and evaluated. Thereby evaluation of data-holding characteristic is enabled at an early stage of development, since circuit operation is unnecessary. Hence, process condition can be optimized, and developing time of a semiconductor memory can be reduced.

9. 发明专利

JP2001291778A METHOD AND DEVICE FOR EXTRACTING STATISTICAL MODEL PARAMETER 失效
公开(公告)号：JP2001291778A
公开(公告)日：2001-10-19
申请号：JP2000106695
申请日：2000-04-04
申请人： HITACHI LTD
发明人： MIYAMA MIKAKO , KANBARA SHIRO , NAKURA KOICHI
IPC分类号： G06F17/50 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/00 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for extracting a statistical model parameter for quickly and precisely extracting the model parameter of a BSIM 3 from the measured data of the saturation currents and threshold of an MOS. SOLUTION: In a method for extracting the value of the model parameter of an MOS device to be used at the time of operating circuit simulation, a model parameter extracted from the Vds-Ids, Vgs-Ids characteristics of one specific device is used as a base, and a statistical model parameter related with a process indicating the oxide film thickness of the MOS, the doze quantity of a channel, short channel effect reduction infra doze quantity, channel length, and channel width is extracted from the measured data of only the saturation currents and threshold of the other MOS.

10. 发明专利

JPH0697020A PROCESS SIMULATOR 失效
公开(公告)号：JPH0697020A
公开(公告)日：1994-04-08
申请号：JP24450792
申请日：1992-09-14
申请人： HITACHI LTD
发明人： KANBARA SHIRO , MATSUO HITOSHI , SUGAYA MASAHIRO
IPC分类号： H01L21/02 , G06F17/50 , G06F19/00 , H01L21/00 , H01L21/66 , G06F15/20 , G06F15/60
摘要： PURPOSE:To provide a process simulator wherein an optimum mesh structure according to a physical model formula used in each process element simulation can be selected. CONSTITUTION:A mesh generation routine which has been taken into a process simulator reads out a contour line at every layer constituting an element, a diffusion species distribution defined on a mesh point inside every layer and a mesh structure inside a user-generated mesh structure table 8 (1). It generates a fundamental mesh having a structure designated by the contour line in every layer (3). After that, it interpolates a diffusion species amount on the fundamental mesh point by the diffusion species distribution inside every layer which has been input (4). In addition, the fundamental mesh and the diffusion species amount which has been interpolated on the fundamental mesh point are used, and a mesh distribution is optimized by using a mesh optimization algorithm defined at every mesh structure (5). Thereby, an optimum mesh structure according to a physical model formula used to compute each simulation can be performed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式