专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0935283A3 Silicone polymer insulation film on semiconductor substrate and method for forming the film 审中-公开
标题翻译：在半导体基板上的有机硅聚合物绝缘膜及其制造方法
公开(公告)号：EP0935283A3
公开(公告)日：2005-06-15
申请号：EP99300841.6
申请日：1999-02-04
申请人： ASM JAPAN K.K.
发明人： Matsuki, Nobuo
IPC分类号： H01L21/312 , H01L21/66 , C23C16/40
CPC分类号： B05D1/62 , C09D4/00 , C23C16/30 , C23C16/401 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/3121 , H01L21/3122 , H01L23/296 , H01L2924/0002 , H01L2924/12044 , Y10S257/914 , C08G77/00 , H01L2924/00
摘要： A method for forming a silicone polymer insulation film having low relative dielectric constant, high thermal stability and high humidity-resistance on a semiconductor substrate is applied to a plasma CVD apparatus. The first step is directly vaporizing a silicon-containing hydrocarbon compound expressed by the general formula Si α O β C x H y (α, β, x, and y are integers) and then introducing the vaporized compound to the reaction chamber of the plasma CVD apparatus. The silicon-containing hydrocarbon compound has at most two O-C n H 2n+1 bonds and at least two hydrocarbon radicals bonded to the silicon. The next step is introducing additive gas into the reaction chamber. The residence time of the material gas is lengthened by reducing the total flow of the reaction gas, in such a way as to forme a silicone polymer film having a micropore porous structure with low relative dielectric constant.

2. 发明公开

EP1114807A1 COMPOSITE MATERIAL AND SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译： EINEN VERBUNDWERKSTOFF VERWENDENDES HALBLEITERBAUTEIL ODERWÄRMEABLEITENDESSUBSTRATDAFÜR
公开(公告)号：EP1114807A1
公开(公告)日：2001-07-11
申请号：EP00937198.0
申请日：2000-06-08
申请人： Sumitomo Electric Industries, Ltd. , Fukui, Akira
发明人： FUKUI, Akira, Itami Works , YAMAGATA, Shinichi, Itami Works , KAMITAKE, Kazuya, Itami Works , ABE, Yugaku, Itami Works
IPC分类号： C04B41/88
CPC分类号： H01L23/3731 , C04B35/573 , C04B41/009 , C04B41/5096 , C04B41/51 , C04B41/85 , C04B41/88 , C04B2111/00844 , H01L23/147 , H01L23/15 , H01L23/3733 , H01L23/3738 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/32188 , H01L2224/32245 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2924/01019 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16195 , H01L2924/181 , Y10S257/914 , Y10T428/249953 , Y10T428/249956 , Y10T428/249957 , C04B41/4523 , C04B35/00 , H01L2924/00014 , H01L2924/00 , H01L2924/2076 , H01L2924/00012
摘要： A composite material that consists mainly of ceramic and semi-metal, that is high in thermal conductivity, that is light in weight, and that has high compatibility in coefficient of thermal expansion (CTE) with a semiconductor element and another member comprising ceramic; a member comprising this composite material; and a semiconductor device comprising the member. The composite material has a structure in which the interstices of a three-dimensional network structure comprising ceramic are filled with a semi-metal-containing constituent produced by deposition after melting, has a CTE of 6 ppm/°C or less, and has a thermal conductivity of 150 W/m·K or more. The semiconductor device comprises the composite material. The composite material can be obtained by filling the pores of a porous body consisting mainly of ceramic with a semi-metal-containing constituent.
摘要翻译：主要由陶瓷和半金属组成的复合材料，其导热性高，重量轻，并且与半导体元件和包含陶瓷的另一个构件具有高热膨胀系数（CTE）的高相容性; 包含该复合材料的构件; 以及包括该构件的半导体器件。复合材料具有这样的结构，其中包含陶瓷的三维网状结构的间隙填充有熔融后沉积产生的含半金属的组分，其CTE为6ppm /℃以下，并且具有导热系数为150 W / mK以上。半导体器件包括复合材料。复合材料可以通过填充主要由具有半金属成分的陶瓷组成的多孔体的孔隙来获得。

3. 发明公开

EP0519830A3 Hemt type semiconductor device 失效
标题翻译： HEMT型半导体器件
公开(公告)号：EP0519830A3
公开(公告)日：1993-03-10
申请号：EP92401714.8
申请日：1992-06-19
申请人： FUJITSU LIMITED
发明人： Takikawa, Masahiko, c/o FUJITSU LIMITED
IPC分类号： H01L29/76 , H01L29/08 , H01L27/095
CPC分类号： H01L27/0605 , H01L27/092 , H01L29/7783 , Y10S257/914
摘要： A HEMT type semiconductor device comprising: a semiconductor substrate (1, 31); a buffer semiconductor layer (2, 32) formed on the substrate; a first semiconductor well layer (3, 33) formed on the buffer layer and serving as a first conductivity type channel layer; a second semiconductor well layer (4, 34) formed on the first well layer and serving as a second conductivity type opposite the first conductivity, channel layer; and a potential barrier layer (5, 35) formed on the second well layer and forming a potential barrier for carriers. The substrate (1, 31) is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

4. 发明公开

EP0496639A3 Polysilicon thin film semiconductor device 失效
标题翻译：多晶硅薄膜半导体器件
公开(公告)号：EP0496639A3
公开(公告)日：1992-12-30
申请号：EP92300639.9
申请日：1992-01-24
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Seto, Shunsuke, c/oIntell. Prop. Div. K.K. Toshiba , Nozaki, Hidetoshi, c/o Intel.Prop.Div. K.K.Toshiba , Mori, Kazushige, c/o Intel.Prop.Div. K.K. Toshiba
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66757 , H01L21/0242 , H01L21/02532 , H01L21/0262 , H01L29/78675 , Y10S257/914
摘要： A polysilicon film pattern (22) of a first conductivity type is formed on one main surface of a substrate (21). A gate electrode (25G) is formed on a predetermined region of the pattern (22) with a gate insulating film (24) interposed therebetween. A source region (23S) and a drain region (23D) of a second conductivity type are formed in the upper portions of the pattern (22). These regions are separated by a region of the pattern located under the gate electrode (25G), and are connected to a source electrode (25S) and a drain electrode (25D), respectively. The electrodes are electrically insulated from each other by means of an interlayer insulating film (26). The polysilicon film pattern (22) contains nitrogen, whose concentration is, in that particular region of the polysilicon film pattern which extends from half of the thickness thereof to the bottom thereof, set higher than that of nitrogen inevitably contained in a polysilicon film formed by a CVD method, and set so as to restrain the formation of silicon crystal nuclei. Further, the pattern (22) is formed by subjecting an amorphous silicon film having the same nitrogen concentration distribution as above, to a solid-phase growth process.

5. 发明公开

EP0103934A2 Insulated-gate field-effect transistors 失效
标题翻译：场效应绝缘栅晶体管。
公开(公告)号：EP0103934A2
公开(公告)日：1984-03-28
申请号：EP83201338.7
申请日：1983-09-19
申请人： PHILIPS ELECTRONICS UK LIMITED , Philips Electronics N.V.
发明人： Coe, David James
IPC分类号： H01L29/78 , H01L27/06
CPC分类号： H01L29/7802 , H01L27/0716 , H01L29/41741 , H01L29/7395 , Y10S257/914
摘要： An insulated-gate field-effect transistor which may be of a vertical power D-MOS type comprises surface-adjacent source and emitter regions (10 and 15) surrounded in a semiconductor body (1) by a surface-adjacent second region (20) of opposite conductivity type. A third region (30) adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of these second and third regions is located in a main current path from the source region (10) to a drain (31) of the transistor, and an insulated gate (4) which may be of metal-silicide capacitively controls a conductive channel at least in this part (21) of the second region (20). The emitter region (15) is located at a side of the source region (10) remote from the channel part (21) and is separated therefrom by an intermediate part (22) of the second region (20). The source region is electrically connected to this intermediate part (22), for example by a short-circuiting metal-silicide layer (8). A resistive current path (25) in the second region (20) is present below the emitter region (10) and extends from this intermediate part (22) to a further part (23) of the second region (20) which is electrically connected to the emitter region (15), for example by a short-circuiting metal-silicide layer (9). A source electrode (2) is electrically connected to this further part (23) so as to be electrically connected via the resistive current path (25) to the source region (10). The emitter region (15) serves to modulate the conductivity of the third region (30) and so reduce the drain series resistance of the transistor, by charge-carrier injection from the intermediate part (22) when the source-drain current along the resistive current path (25) is sufficient to forward-bias the intermediate part (22) with respect to the third region (30).

6. 发明授权

EP0526212B1 Method of forming isolated regions of oxide 失效
标题翻译：一种用于生产隔离区的氧化过程
公开(公告)号：EP0526212B1
公开(公告)日：2001-02-28
申请号：EP92306967.8
申请日：1992-07-30
申请人： STMicroelectronics, Inc.
发明人： Hodges, Robert , Bryant, Frank
IPC分类号： H01L21/76 , H01L21/32
CPC分类号： H01L21/32 , Y10S148/015 , Y10S148/117 , Y10S257/905 , Y10S257/912 , Y10S257/914

7. 发明公开

EP0849796A2 Improvements in or relating to integrated circuits 失效
标题翻译：改进或与其有关的集成电路
公开(公告)号：EP0849796A2
公开(公告)日：1998-06-24
申请号：EP97310137.1
申请日：1997-12-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jin, Changming , Yamanaka, Stacey , List, R Scott
IPC分类号： H01L23/532
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02214 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76801 , H01L21/76834 , H01L23/5329 , H01L2924/0002 , Y10S257/914 , Y10T428/12528 , Y10T428/31663 , H01L2924/00
摘要： An integrated circuit with an intermetal level dielectric (IMD) including an organic-silica hybrid (110) and located between metal lines (104).
摘要翻译：与金属间电介质（IMD）包括在有机 - 二氧化硅杂化（110）和位于之间的金属线（104）的集成电路。

8. 发明公开

EP0645823A1 Four layer overvoltage protection diode 失效
标题翻译： Vierschicht-Überspannungsschutzdiode。
公开(公告)号：EP0645823A1
公开(公告)日：1995-03-29
申请号：EP94250188.3
申请日：1994-07-25
申请人： TECCOR ELECTRONICS
发明人： Webb, Monty F. , Turner, Elmer L.
IPC分类号： H01L29/86
CPC分类号： H01L29/87 , Y10S257/914
摘要： An overvoltage protection device having multiple shorting dots (66) in the emitter region and multiple buried regions (72) substantially aligned with these shorting dots. The placement, number, and area of these buried regions reduce and more accurately set the overshoot voltage value of the device while maintaining the high surge capacities of the device. Further, doping types and concentrations have been modified from that known in the prior art to reduce overshoot providing a more accurate and sensitive overvoltage protection device than that known previously in the prior art.
The emitter regions (68) are preferably p⁺⁺ doped, the upper base (70) is n⁺ doped, the mid-region layer (74) is p-doped, with the burred regions (72) being p⁺ doped, the lower base region (76) is n⁺ doped and contains a "getter" region (78) of higher doping to reduce the leakage current.
摘要翻译：在发射极区域具有多个短路点（66）的过电压保护装置和与这些短路点基本对准的多个埋入区域（72）。这些掩埋区域的布置，数量和面积减小并且更精确地设置器件的过冲电压值，同时保持器件的高浪涌能力。此外，掺杂类型和浓度已经从现有技术中已知的掺杂类型和浓度进行了修改，以减少过冲，提供比现有技术中先前已知的过电压保护器件更精确和更灵敏的过电压保护器件。发射极区域（68）优选为掺杂p + +，上部基底（70）为n +掺杂，中间区域层（74）为p掺杂，其中，被掺杂的p +，下基极区域（76）是n +掺杂的，并且含有较高掺杂的“吸气剂”区域（78）以减少漏电流。

9. 发明授权

EP0327859B1 A vertical isolated-collector transistor of the PNP type incorporating a device for suppressing the effects of parasitic junction components 失效
标题翻译： PNP型与具有排列分离的收集器中，为了抑制寄生过渡元素的效果的垂直晶体管。
公开(公告)号：EP0327859B1
公开(公告)日：1995-03-01
申请号：EP89100945.8
申请日：1989-01-20
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Siligoni, Marco , Villa, Flavio
IPC分类号： H01L29/72
CPC分类号： H01L29/7302 , H01L29/0826 , H01L29/7322 , Y10S257/914 , Y10S257/918

10. 发明公开

EP0526212A2 Method of forming isolated regions of oxide 失效
标题翻译： Verfahren zur Herstellung von Isolationszonen aus Oxid。
公开(公告)号：EP0526212A2
公开(公告)日：1993-02-03
申请号：EP92306967.8
申请日：1992-07-30
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Hodges, Robert , Bryant, Frank
IPC分类号： H01L21/76 , H01L21/32
CPC分类号： H01L21/32 , Y10S148/015 , Y10S148/117 , Y10S257/905 , Y10S257/912 , Y10S257/914
摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over the integrated circuit. A nitrogen doped polysilicon layer is formed over the pad oxide layer. A thick nitride layer is then formed over the nitrogen doped polysilicon layer. An opening is formed in the nitride layer and the nitrogen doped polysilicon layer exposing a portion of the pad oxide layer. The nitrogen doped polysilicon layer is annealed encapsulating the polysilicon layer in silicon nitride. A field oxide region is then formed in the opening.
摘要翻译：提供一种用于形成集成电路的隔离氧化物区域的方法，以及根据该集成电路形成的集成电路。在集成电路上形成衬垫氧化物层。在衬垫氧化物层上形成氮掺杂多晶硅层。然后在氮掺杂多晶硅层上形成厚的氮化物层。在氮化物层和氮掺杂多晶硅层中形成一个开口，暴露一部分焊盘氧化物层。氮掺杂多晶硅层退火，将多晶硅层封装在氮化硅中。然后在开口中形成场氧化物区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式