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1. 发明公开

EP4373233A2 A THERMALIZATION ARRANGEMENT AT CRYOGENIC TEMPERATURES 审中-公开
公开(公告)号：EP4373233A2
公开(公告)日：2024-05-22
申请号：EP24168258.2
申请日：2022-02-18
申请人： Teknologian Tutkimuskeskus VTT OY
发明人： PRUNNILA, Mika , RONZANI, Alberto , MYKKÄNEN, Emma , KEMPPINEN, Antti , LEHTINEN, Janne
IPC分类号： H05K7/20
CPC分类号： F28F2013/00620130101 , H05K7/20481 , H05K7/20372 , H01L23/3738
摘要： An inventive embodiment comprises a thermalization arrangement at cryogenic temperatures. The arrangement comprises a dielectric substrate (2) layer on which substrate a device/s or component/s (1) are positionable. A heat sink component (4) is attached on another side of the substrate. The arrangement further comprises a conductive layer (5) between the substrate layer (2) and the heat sink component (4). A joint between the substrate layer (2) and the conductive layer (5) has minimal thermal boundary resistance. Another joint between the conductive layer (5) and the cooling heat sink layer (4) is electrically conductive.

2. 发明公开

EP3216053A1 SILICON PACKAGE FOR EMBEDDED SEMICONDUCTOR CHIP AND POWER CONVERTER 审中-公开
标题翻译：硅包装嵌入式半导体芯片和电力转换器
公开(公告)号：EP3216053A1
公开(公告)日：2017-09-13
申请号：EP15857773.4
申请日：2015-11-06
申请人： Texas Instruments Incorporated
发明人： LOPEZ, Osvaldo, Jorge , NOQUIL, Jonathan, Almeria , GREBS, Tom , MOLLOY, Simon, John
IPC分类号： H01L23/485 , H01L21/50
CPC分类号： H01L23/147 , H01L21/481 , H01L21/4846 , H01L23/13 , H01L23/3738 , H01L24/83 , H01L24/97 , H01L2224/06181 , H01L2224/32225 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/15153 , H01L2924/157
摘要： A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
摘要翻译：封装的晶体管器件（100）包括：半导体芯片（101），其包括具有分布在第一和相对的第二芯片侧上的端子的晶体管; 和构造为脊（111）的低等级硅（Ig-Si）的板（110），所述脊构成凹陷，所述凹陷包括适于容纳所述芯片的凹陷的中心区域，所述脊具有在第一平面中的第一表面，中央区域在第二平面中具有第二平面，第二平面与第一平面间隔开至少等于芯片厚度的深度（112），所述脊状物被连接到中央区域中的连接垫的器件端子（120; 121）覆盖，连接第一芯片侧的端子，使得相对的第二芯片侧的端子（103）与平板脊上的器件端子共面。

3. 发明公开

EP2733181A4 RESIN COMPOSITION FOR A SURFACE TREATMENT, AND STEEL SHEET COATED WITH SAME 审中-公开
标题翻译：表面处理的树脂组合物，因此涂层钢板
公开(公告)号：EP2733181A4
公开(公告)日：2015-08-05
申请号：EP12810861
申请日：2012-07-13
申请人： POSCO , NOROO COIL COATINGS CO LTD
发明人： JUNG YONG-GYUN , KIM GAB-YONG , KIM WOON-JONG , CHO JAE-DONG , KIM JONG-SANG , KIM JOONG-KYU , CHOI MYOUNG-HEE , SONG YON-KYUN
IPC分类号： C09D7/12 , C09D201/00 , C23C26/00 , H01B1/22 , H01L23/373
CPC分类号： C09D5/24 , C09D7/61 , C09D7/68 , C09D7/69 , H01L23/373 , H01L23/3735 , H01L23/3737 , H01L23/3738 , H01L2924/0002 , Y10T428/24975 , Y10T428/25 , Y10T428/256 , Y10T428/259 , Y10T428/265 , Y10T428/31529 , Y10T428/31605 , H01L2924/00
摘要： Provided are a resin composition for surface treatment and a surface-treated steel sheet coated therewith. The resin composition for surface treatment includes a dispersing element having excellent thermal conductivity and heat dissipation, thereby maintaining physical properties of the conventional anti-fingerprint steel sheet, for example, high whiteness, fingerprint resistance, workability, electric conductivity and alkali resistance, and providing heat dissipation. In addition, the surface-treated steel sheet coated with the resin composition for surface treatment of the present invention has physical properties such as high heat dissipation, electric conductivity and whiteness, and thus may be replaced with a bottom chassis of a backlight unit, particularly, an edge-type backlight unit.

4. 发明公开

EP2428995A3 Gallium Nitride Based Semiconductor Devices and Methods of Manufacturing the Same 审中-公开
标题翻译：氮化镓基半导体器件及其制备方法
公开(公告)号：EP2428995A3
公开(公告)日：2013-05-29
申请号：EP11180298.9
申请日：2011-09-07
申请人： Samsung Electronics Co., Ltd.
发明人： Lee, Jae-hoon , Kim, Ki-se
IPC分类号： H01L29/778 , H01L23/373 , H01L21/335
CPC分类号： H01L23/373 , H01L23/3731 , H01L23/3736 , H01L23/3738 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L29/872 , H01L2224/13 , H01L2924/12032 , H01L2924/00
摘要： Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.

5. 发明公开

EP1972008A4 SILICON CARBIDE DIMPLED SUBSTRATE 审中-公开
标题翻译： GEKRÄUSELTESSILICIUMCARBIDSUBSTRAT
公开(公告)号：EP1972008A4
公开(公告)日：2011-03-23
申请号：EP07709682
申请日：2007-01-10
申请人： CREE INC
发明人： HARRIS CHRISTOPHER , BASCERI CEM , GEHRKE THOMAS , BALKAS CENGIZ
IPC分类号： H01L21/84 , H01L33/00 , H01L33/32 , H01L33/38
CPC分类号： H01L33/38 , H01L21/0475 , H01L23/367 , H01L23/3738 , H01L29/0657 , H01L29/1608 , H01L29/20 , H01L29/2003 , H01L29/417 , H01L33/0079 , H01L33/32 , H01L2924/0002 , H01L2924/10158 , H01L2933/0016 , H01L2924/00
摘要： A substrate is disclosed. It comprises: a first layer having a first main surface and a second main surface opposing the first main surface; an active layer on the first main surface of the first layer; an array of dimples extending from the second main surface into the first layer toward the first main surface; and a metallization layer overlying the second main surface of the first layer and within the dimples.

6. 发明公开

EP1256129A4 SPONTANEOUS EMISSION ENHANCED HEAT TRANSPORT METHOD AND STRUCTURES FOR COOLING, SENSING, AND POWER GENERATION 审中-公开
标题翻译：随着对COOL，交易会和发电量增加自发辐射与STRUKUTREN热传输方法
公开(公告)号：EP1256129A4
公开(公告)日：2007-04-04
申请号：EP01995957
申请日：2001-11-29
申请人： RES TRIANGLE INST
发明人： VENKATASUBRAMANIAN RAMA
IPC分类号： H01L23/36 , F25B21/02 , G06F1/16 , G06F1/20 , H01L23/34 , H01L23/373 , H01L23/38 , H01L35/00 , H01L35/08 , H01L35/30 , H01S5/024 , H01S5/183 , F25B23/00
CPC分类号： H01L35/30 , F25B21/02 , G06F1/1632 , G06F1/20 , G06F1/203 , H01L23/34 , H01L23/3738 , H01L23/38 , H01L35/00 , H01L35/08 , H01L2225/06589 , H01L2924/0002 , Y10S257/93 , H01L2924/00
摘要： A method and structure for heat transport, cooling, sensing and power generation is described. A photonic bandgap structure ( 3 ) is employed to enhance emissive heat transport from heat sources such as integrated circuits ( 2 ) to heat spreaders ( 4 ). The photonic bandgap structure ( 3 ) is also employed to convert heat to electric power by enhanced emission absorption and to cool and sense radiation, such as infra-red radiation. These concepts may be applied to both heat loss and heat absorption, and may be applied to heat transport and absorption enhancement in a single device.

7. 发明公开

EP0707741A4 SURFACE MOUNT AND FLIP CHIP TECHNOLOGY 失效
标题翻译： OBERFLÄCHENMONTAGEUND FLIP-CHIP-TECHNOLOGIE
公开(公告)号：EP0707741A4
公开(公告)日：1997-07-02
申请号：EP95918863
申请日：1995-05-04
申请人： SILICONIX INC
发明人： CHANG MIKE F , OWYANG KING , HSHIEH FWU-IUAN , HO YUEH-SE , DUN JOWEI , FUESSER HANS-JUERGEN , ZACHAI REINHARD
IPC分类号： H01L21/822 , H01L23/29 , H01L23/367 , H01L23/373 , H01L23/48 , H01L23/485 , H01L27/04 , H01L21/76
CPC分类号： H01L24/10 , H01L23/29 , H01L23/3672 , H01L23/3732 , H01L23/3738 , H01L23/481 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/73253 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. A heat sink cap (100) is attached to a diamond passivation layer (96) on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. In a flip chip version, frontside electrical contacts (174a, 174b) extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts (90a, 90g) formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.
摘要翻译：集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。散热器盖（100）附着到基板前侧表面上的金刚石钝化层（96）。钝化层是提供电绝缘和导热性的CVD金刚石膜。在倒装芯片版本中，前侧电触点（174a，174b）延伸穿过前侧钝化层到散热器盖。在表面安装型式中，通孔穿过基板，其中形成在通孔上的表面安装柱（90a，90g）接触前侧电触头并提供在基板背面上的所有电触点。然后将晶片以两个版本划片成模具，而不需要进一步的包装。

8. 发明授权

EP0471552B1 Heat transfer module for ultra high density and silicon on silicon packaging applications 失效
标题翻译：对于应用的超高密度，硅 - 硅填料热量传输模块
公开(公告)号：EP0471552B1
公开(公告)日：1997-07-02
申请号：EP91307449.8
申请日：1991-08-13
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Ozmat, Burhan
IPC分类号： H01L23/373 , H01L23/473 , H01L23/14
CPC分类号： H01L23/473 , H01L23/147 , H01L23/3733 , H01L23/3738 , H01L2224/16225 , H01L2924/09701

9. 发明公开

EP0683624A2 Narrow channel finned heat sinking for cooling high power electronic components 失效
标题翻译： WärmeabfuhrdurchengkanäligeKühlrippenzurKühlungvon elektronischen Hochleistungskomponenten。
公开(公告)号：EP0683624A2
公开(公告)日：1995-11-22
申请号：EP95112492.4
申请日：1992-11-20
申请人： AT&T Corp.
发明人： Azar, Kaveh , Caron, Richard Edward
IPC分类号： H05K7/20
CPC分类号： F28F3/02 , H01L23/367 , H01L23/3731 , H01L23/3736 , H01L23/3738 , H01L23/467 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Dissipation of the heat produced by the operation of electronic circuitry may be improved by a heat sink which comprises a flat base from which a number of vertical fins extend. The fins are parallel to one another and define a number of parallel channels into which coolant flow is directed. The thermal resistance of the heat sink is optimized by setting fin thickness and channel width parameters to appropriate values. The heat sink may be attached in a heat conductive manner to a heat producing electronic component. One or more of these heat sinked components may be laid out in an in-line or staggered arrangement on a support in the form of a circuit pack. Cooling fluid is delivered to the circuit pack in a variety of ways to cool the heat sinked components. A method of determining the optimum fin thickness and channel width parameters involves determining a relationship between total thermal resistance of the heat sink and combinations of fin thickness and channel width parameters. A contour plot is produced in accordance with the relationship referred to above. The contour plot shows regions of optimum heat dissipation for heat sinks in accordance with the geometry identified here.
摘要翻译：通过电子电路的操作产生的热量的消散可以通过散热器来改善，所述散热器包括多个垂直散热片从该底板延伸的平坦基座。散热片彼此平行并且限定冷却剂流引导到的多个平行通道。通过将翅片厚度和通道宽度参数设置为适当的值来优化散热器的热阻。散热器可以以导热的方式附接到发热电子部件。这些散热部件中的一个或多个可以以线性或交错布置布置在电路板形式的支撑件上。冷却液以各种方式输送到电路板，以冷却散热部件。确定最佳翅片厚度和通道宽度参数的方法包括确定散热器的总热阻与翅片厚度和通道宽度参数的组合之间的关系。根据上述关系产生等高线图。轮廓图根据这里识别的几何图形显示散热器的最佳散热区域。

10. 发明公开

EP3216053A4 SILICON PACKAGE FOR EMBEDDED SEMICONDUCTOR CHIP AND POWER CONVERTER 审中-公开
公开(公告)号：EP3216053A4
公开(公告)日：2018-07-11
申请号：EP15857773
申请日：2015-11-06
申请人： TEXAS INSTRUMENTS INC
发明人： LOPEZ OSVALDO JORGE , NOQUIL JONATHAN ALMERIA , GREBS TOM , MOLLOY SIMON JOHN
IPC分类号： H01L23/485 , H01L21/50 , H01L23/13 , H01L23/14
CPC分类号： H01L23/147 , H01L21/481 , H01L21/4846 , H01L23/13 , H01L23/3738 , H01L24/83 , H01L24/97 , H01L2224/06181 , H01L2224/32225 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/15153 , H01L2924/157
摘要： A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

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