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1. 发明授权

EP2661773B1 SEMICONDUCTOR DEVICE ARRANGEMENT WITH A FIRST SEMICONDUCTOR DEVICE AND WITH A PLURALITY OF SECOND SEMI CONDUCTOR DEVICES 有权
标题翻译：半导体器件与第一半导体器件和多第二半导体器件安排
公开(公告)号：EP2661773B1
公开(公告)日：2016-03-23
申请号：EP12700220.2
申请日：2012-01-09
申请人： Infineon Technologies Austria AG
发明人： WEIS, Rolf , HIRLER, Franz , FELDTKELLER, Martin , DEBOY, Gerald , STECHER, Matthias , WILLMEROTH, Armin
IPC分类号： H01L27/088 , H01L27/06 , H01L29/78 , H01L29/40 , H01L27/07 , G05F1/573 , H01L27/02 , H02H9/02
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06

2. 发明公开

EP2933835A1 RF power transistor 审中-公开
标题翻译： RF-Leistungstransistor
公开(公告)号：EP2933835A1
公开(公告)日：2015-10-21
申请号：EP14164753.7
申请日：2014-04-15
申请人： NXP B.V.
发明人： Zhu, Yi
IPC分类号： H01L23/66 , H01L23/00 , H03F1/56 , H01L23/64
CPC分类号： H01L23/49589 , H01L23/4952 , H01L23/64 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/7817 , H01L2223/6611 , H01L2223/6655 , H01L2224/05599 , H01L2224/45124 , H01L2224/48096 , H01L2224/48097 , H01L2224/48195 , H01L2224/48247 , H01L2224/4909 , H01L2224/49109 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/19107 , H03F1/565 , H03F3/193 , H03F2200/387 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device including an RF power transistor in a semiconductor package is described. The semiconductor device comprises a gate lead frame, a drain lead frame, a die including a power transistor having a gate and a drain and a flange. A gate impedance matching network is connected between the gate lead frame and the gate. A drain impedance matching network is connected between the drain lead frame and the drain and includes a drain lead frame bond wire between the drain lead frame and the drain. A first conducting element is connected between the die and the flange and is arranged to provide a current path along which a return current can flow in use to lower an inductance associated with the drain lead frame bond wire.
摘要翻译：描述了包括半导体封装中的RF功率晶体管的半导体器件。该半导体器件包括栅极引线框架，漏极引线框架，包括具有栅极和漏极的功率晶体管和法兰的管芯。栅极引线框架和栅极之间连接有栅极阻抗匹配网络。漏极阻抗匹配网络连接在漏极引线框架和漏极之间，并且在漏极引线框架和漏极之间包括漏极引线框架接合线。第一导电元件连接在模具和凸缘之间，并且被布置成提供电流路径，在使用中电流可以流过，以降低与漏极引线框架接合线相关联的电感。

3. 发明公开

EP2838194A1 Amplifier circuits 失效转让
标题翻译： Verstärkerschaltungen
公开(公告)号：EP2838194A1
公开(公告)日：2015-02-18
申请号：EP13290190.1
申请日：2013-08-14
申请人： NXP B.V.
发明人： Bouisse, Gerard
IPC分类号： H03F3/193 , H03F3/45 , H01L27/07
CPC分类号： H03F3/45179 , H01L27/0705 , H01L27/088 , H01L29/7817 , H01L2224/49175 , H03F3/193 , H03F3/21 , H03F3/265 , H03F3/45 , H03F3/45183 , H03F2200/06 , H03F2200/255 , H03F2203/45356 , H03F2203/45481
摘要： Differential amplifier circuits for LDMOS-based amplifiers are disclosed. The differential amplifier circuits comprise a high resistivity substrate and separate DC and AC ground connections. Such amplifier circuits may not require thrusubstrate vias for ground connection.
摘要翻译：公开了用于基于LDMOS的放大器的差分放大器电路。差分放大器电路包括高电阻衬底和单独的DC和AC接地连接。这种放大器电路可能不需要用于接地连接的路基通孔。

4. 发明公开

EP2731144A3 Semiconductor device and driver circuit with an active device and isolation structure interconnected through a resistor circuit, and method of manufacture thereof 有权
标题翻译：半导体器件，并与活性组分的驱动电路，并且经由电阻器电路隔离结构连接和相关联的制造过程
公开(公告)号：EP2731144A3
公开(公告)日：2014-12-31
申请号：EP13191777.5
申请日：2013-11-06
申请人： Freescale Semiconductor, Inc.
发明人： Bode, Hubert , Chen, Weize , De Souza, Richard J. , Parris, Patrice M.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L21/761
CPC分类号： H01L21/761 , H01L29/0653 , H01L29/0847 , H01L29/0869 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66689 , H01L29/7817 , H01L29/7818 , H01L29/782 , H01L29/7835
摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate (1510) having a first conductivity type, an isolation structure (including a sinker region (1522) and a buried layer (1520)), an active device (1462, 1463, 1500, 1600, 1700, 1800, 1900, 2000) within a portion (1530) of the substrate contained by the isolation structure, and a resistor circuit (1546, 1646, 1746, 1846, 1946, 2046). The buried layer is positioned below the top substrate surface (1512), and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region (1534), which is separated from the isolation structure by a portion (1537) of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode (1710, 1810) and/or one or more PN diode(s) (1910, 2010) in series and/or parallel with the resistor network(s).

5. 发明公开

EP2765604A1 HIGH-VOLTAGE DEVICE OF COMPOSITE STRUCTURE AND STARTING CIRCUIT 审中-公开
标题翻译：爱尔兰VERBUNDSTRUKTUR UNLAUFSCHALTUNG的HOCHSPANNUNGSVORRICHTUNG
公开(公告)号：EP2765604A1
公开(公告)日：2014-08-13
申请号：EP13840111.2
申请日：2013-08-09
申请人： Shenzhen Sunmoon Microelectronics Co. Ltd.
发明人： LI, Zhaohua
IPC分类号： H01L27/02 , H01L27/088 , H01L27/098 , H03K3/353
CPC分类号： H01L29/0623 , H01L27/0203 , H01L27/085 , H01L29/7817 , H01L29/7832 , H01L29/7835 , H01L29/808 , H02M1/36 , H03K17/22
摘要： An embodiment of the invention provides a high voltage device with composite structure. The high voltage device with composite structure comprises a high voltage power MOS transistor HVNMOS and a JFET. The high voltage power MOS transistor HVNMOS comprises a drain, a source, a gate and a substrate, and a P-type well region Pwell as a conducting channel which is arranged between the source and the drain. The JFET comprises the drain, the source, the gate and the substrate, and an N-type well region Nwell as a conducting channel which is arranged between the source and the drain. The high voltage power MOS transistor HVNMOS and the JFET share the same drain, and the drain is processed by using N-type double diffusion process. The embodiment of the present invention further presents a starting circuit using the high voltage device with composite structure. The above solution provided by the embodiment of the present invention effectively saves the chip area and reduces the cost of the chip, due to the composite structure of the high voltage device.
摘要翻译：本发明的一个实施例提供一种具有复合结构的高压装置。具有复合结构的高压器件包括高压功率MOS晶体管HVNMOS和JFET。高压功率MOS晶体管HVNMOS包括漏极，源极，栅极和衬底，以及P型阱区P阱作为布置在源极和漏极之间的导电沟道。 JFET包括漏极，源极，栅极和衬底以及布置在源极和漏极之间的作为导电沟道的N型阱区Nwell。高压功率MOS晶体管HVNMOS和JFET共享相同的漏极，并且通过使用N型双扩散处理来处理漏极。本发明的实施例还提供了一种使用具有复合结构的高电压装置的启动电路。由于高电压装置的复合结构，本发明实施例提供的上述方案有效地节省了芯片面积并降低了芯片的成本。

6. 发明公开

EP2731144A2 Semiconductor device and driver circuit with an active device and isolation structure interconnected through a resistor circuit, and method of manufacture thereof 有权
标题翻译：半导体器件，并与活性组分的驱动电路，并且经由电阻器电路隔离结构连接和相关联的制造过程
公开(公告)号：EP2731144A2
公开(公告)日：2014-05-14
申请号：EP13191777.5
申请日：2013-11-06
申请人： Freescale Semiconductor, Inc.
发明人： Bode, Hubert , Chen, Weize , De Souza, Richard J. , Parris, Patrice M.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L21/761
CPC分类号： H01L21/761 , H01L29/0653 , H01L29/0847 , H01L29/0869 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66689 , H01L29/7817 , H01L29/7818 , H01L29/782 , H01L29/7835
摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate (1510) having a first conductivity type, an isolation structure (including a sinker region (1522) and a buried layer (1520)), an active device (1462, 1463, 1500, 1600, 1700, 1800, 1900, 2000) within a portion (1530) of the substrate contained by the isolation structure, and a resistor circuit (1546, 1646, 1746, 1846, 1946, 2046). The buried layer is positioned below the top substrate surface (1512), and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region (1534), which is separated from the isolation structure by a portion (1537) of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode (1710, 1810) and/or one or more PN diode(s) (1910, 2010) in series and/or parallel with the resistor network(s).
摘要翻译：半导体器件和驱动器电路的实施例包括具有第一导电类型，在隔离结构的半导体基片（1510）（包括下沉区（1522）和埋层（1520））到有源器件（1462，1463，1500， 1600，1700，1800，1900，2000年）由隔离结构包含在衬底的一部分（1530），和一个电阻器电路（1546，1646，1746，1846，1946，2046）内。掩埋层位于顶表面的衬底（1512）的下方，并具有第二导电类型。下沉区域的顶部表面与所述掩埋层基板之间延伸，并且具有第二导电类型。所述有源器件包括从所述隔离结构由具有第一导电类型的半导体衬底的一部分（1537）分开的本体区（1534），所有。电阻电路连接在隔离结构和本体区域之间。电阻器电路可以包括一个或多个电阻器网络，并且任选地，一个肖特基二极管（1710，1810）和/或一个或更多个PN二极管（一个或多个）（1910，2010）（以串联和/或平行于电阻器网络小号）。

7. 发明公开

EP2661773A2 SEMICONDUCTOR DEVICE ARRANGEMENT WITH A FIRST SEMICONDUCTOR DEVICE AND WITH A PLURALITY OF SECOND SEMI CONDUCTOR DEVICES 有权
标题翻译：半导体器件与第一半导体器件和多第二半导体器件安排
公开(公告)号：EP2661773A2
公开(公告)日：2013-11-13
申请号：EP12700220.2
申请日：2012-01-09
申请人： Infineon Technologies Austria AG
发明人： WEIS, Rolf , HIRLER, Franz , FELDTKELLER, Martin , DEBOY, Gerald , STECHER, Matthias , WILLMEROTH, Armin
IPC分类号： H01L27/088 , H01L27/06 , H01L29/78 , H01L29/40 , H01L27/07 , G05F1/573 , H01L27/02 , H02H9/02
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0623 , H01L27/0629 , H01L27/0727 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L27/098 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/4236 , H01L29/4238 , H01L29/78 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/7838 , H03K17/06
摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

8. 发明授权

EP1284019B1 HALBLEITER-LEISTUNGSBAUELEMENT 有权
标题翻译：半导体功率器件
公开(公告)号：EP1284019B1
公开(公告)日：2007-09-26
申请号：EP01940224.7
申请日：2001-05-10
申请人： ROBERT BOSCH GMBH
发明人： FEILER, Wolfgang
IPC分类号： H01L29/06 , H01L29/735 , H01L29/739
CPC分类号： H01L29/405 , H01L27/0629 , H01L28/20 , H01L29/063 , H01L29/7393 , H01L29/7817
摘要： At least one polysilicon (Si) resistor (5) is provided for the transmission of signals between a high voltage side (2) and a low voltage side (3) of a semiconductor power component (1) having a REduced SURface Field (RESURF) area (4) . Said polysilicon resistor is arranged above the RESURF area (4) and is electrically insulated therefrom, resulting in a high withstand strength with respect to blocking voltage.

9. 发明公开

EP0565808A1 Junction-isolated high voltage MOS integrated device 失效
标题翻译：接头分离器，Hochspannungsintegriertes MOS-Bauelement。
公开(公告)号：EP0565808A1
公开(公告)日：1993-10-20
申请号：EP92830190.2
申请日：1992-04-17
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Ravanelli, Enrico Maria Alfons , Villa,Flavio
IPC分类号： H01L29/06
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/404 , H01L29/7801 , H01L29/7817
摘要： An integrated device comprising isolating regions (18) of a first type of conductivity, each surrounding an epitaxial pocket (8) of an opposite type of conductivity, housing drain and source regions, and covered with an oxide layer (22a, 22b) housing gate regions (7) and over which extend the source (31), drain and gate connections. For linearizing potential distribution at the epitaxial pocket (8)- isolating region (18) junction and close to the source regions beneath the connections (31), these regions are provided with a double chain of condensers (11, 12) embedded in the oxide layer (22a, 22b) and the terminal elements (12a, 11a) and the intermediate element (11b) of which are biased to predetermined potentials (V G , ground, V D ).
摘要翻译：一种集成器件，包括隔离第一导电类型的区域（18），每个区域围绕具有相反导电类型的外延腔（8），容纳漏极和源极区域，并且覆盖有容纳栅极的氧化物层（22a，22b）区域（7）和其上延伸源（31），漏极和栅极连接。为了线性化外延阱（8） - 隔离区（18）结处并且靠近连接（31）下方的源极区的电位分布，这些区域设置有嵌入氧化物中的双链冷凝器（11,12）层（22a，22b）和端子元件（12a，11a）和中间元件（11b）偏置到预定电位（VG，接地，VD）。

10. 发明公开

EP0360991A2 An integrated circuit self-protected against reversal of the supply battery polarity 失效
标题翻译：该集成电路是自保护，以防止供给电池的极性反转。
公开(公告)号：EP0360991A2
公开(公告)日：1990-04-04
申请号：EP89112711.0
申请日：1989-07-12
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Contiero, Claudio , Murari, Bruno
IPC分类号： H02H11/00 , H01L27/02
CPC分类号： H01L29/7803 , H01L27/0218 , H01L27/0266 , H01L29/0878 , H01L29/42368 , H01L29/7809 , H01L29/7817 , H01L29/7831 , H02H11/003 , Y10T307/839
摘要： An integrated circuit (1) self-protected agianst reversal of the supply battery (2) polarity comprises a first DMOS power transistor (T1) connected with its source electrode (S1) side to an electric load (R1) to be driven toward ground, and a second, protective DMOS transistor (T2) which is connected with its source electrode (S2) side to a positive pole (Vc) of the battery (2) and with its drain electrode (D2) side to the drain electrode (D1) of the first transistor (T1). The first T1) and second (T2) transistors have in common the drain region formed on a single pod (9) in the semiconductor substrate (4).
摘要翻译：一种集成电路（1）自保护agianst供给电池的逆转（2）极性包括与它的源极电极（S1）侧连接到在电负载（R1）的第一DMOS功率晶体管（T1）为朝向地面驱动，和第二保护DMOS晶体管（T2）的所有其与它的源极（S2）侧连接到电池（2），并用它的漏极（D2）侧到漏极电极的正极（VC）（D1）第一晶体管（T1）的。第一T1）和第二（T2）的晶体管具有共同形成在半导体衬底（4）的单个盒（9）的漏区。

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