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1. 发明授权

EP2380199B1 BIAS VOLTAGE GENERATION CIRCUIT FOR AN SOI RADIO FREQUENCY SWITCH 有权转让
标题翻译：偏置电压SOI RF开关
公开(公告)号：EP2380199B1
公开(公告)日：2015-01-21
申请号：EP09835568.8
申请日：2009-12-15
申请人： International Business Machines Corporation
发明人： BOTULA, Alan, B. , NOWAK, Edward, J.
IPC分类号： H03K17/693 , H01L27/12 , H01P1/15
CPC分类号： H01L27/1203 , H01L27/0218 , H01P1/15 , H03K17/693 , H03K2217/0018

2. 发明公开

EP2380199A4 BIAS VOLTAGE GENERATION CIRCUIT FOR AN SOI RADIO FREQUENCY SWITCH 有权转让
标题翻译：偏置电压SOI RF开关
公开(公告)号：EP2380199A4
公开(公告)日：2012-02-29
申请号：EP09835568
申请日：2009-12-15
申请人： IBM
发明人： BOTULA ALAN B , NOWAK EDWARD J
IPC分类号： H03K17/693 , H01L27/12 , H01P1/15
CPC分类号： H01L27/1203 , H01L27/0218 , H01P1/15 , H03K17/693 , H03K2217/0018

3. 发明授权

EP0545604B1 High-withstand voltage integrated circuit 无效
标题翻译：具有高耐受电压的集成电路
公开(公告)号：EP0545604B1
公开(公告)日：2004-11-10
申请号：EP92310730.4
申请日：1992-11-24
申请人： FUJI ELECTRIC CO. LTD.
发明人： Fijihira, Tatsuhiko , Nishiura, Masaharu
IPC分类号： H01L27/02 , H01L27/088
CPC分类号： H01L27/088 , H01L27/0218

4. 发明授权

EP0739097B1 MOSFET circuit and CMOS logic circuit using the same 失效
标题翻译： MOSFET电路及其在CMOS逻辑电路中的应用
公开(公告)号：EP0739097B1
公开(公告)日：2004-04-07
申请号：EP96106128.0
申请日：1996-04-18
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： Douseki, Takakuni
IPC分类号： H03K19/00 , H03K19/003 , H03K19/017
CPC分类号： H03K19/0016 , H01L27/0218 , H03K19/00361

5. 发明授权

EP0701737B1 METHOD OF FORMING A PLURALITY OF TRANSISTORS IN A SUBSTRATE. 失效
标题翻译：在衬底中制造多个晶体管的方法，
公开(公告)号：EP0701737B1
公开(公告)日：2003-05-28
申请号：EP95914892.5
申请日：1995-03-24
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： MERRILL, Richard, B. , YOUNG, Whu-ming
IPC分类号： H01L27/02 , H01L27/092
CPC分类号： H01L29/0847 , H01L27/0218 , H01L27/0222 , H01L27/092 , H01L27/0928 , H01L29/1083 , H01L29/1087 , H01L29/7835 , H02M3/07
摘要： A cascaded charge pump circuit comprising a plurality of charge pumps (140, 142 etc), each having three output terminals with a small (three volt) increment between outputs. The output terminals are connected to successive nodes (150, 152 etc) in a string and pairs of adjacent nodes are connected by switching elements which provide an output clock signal, switching between the voltages at the respective pair of nodes, the various clock signals being used to drive the charge pump stages.

6. 发明公开

EP0805557A3 Semiconductor integrated circuit device 失效
标题翻译：设备集成半导体电路
公开(公告)号：EP0805557A3
公开(公告)日：1999-04-07
申请号：EP97107187.3
申请日：1997-04-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kuroda, Tadahiro , Sakurai, Takayasu
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H01L27/0218 , H01L2224/05554 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/13091 , H01L2924/3011 , H01L2924/30111 , H03K19/00384 , H03K19/018507 , H01L2924/00 , H01L2224/45099
摘要： To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit (1) for generating a predetermined voltage fixed between a first supply voltage (GND) and a second supply voltage (V DD ); a driver circuit (5) for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit (1) and the first supply voltage (GND), and for driving a transfer path by the converted signal; a voltage divider circuit (9) for dividing an output voltage of the bias circuit; and a receiver circuit (10) for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.

7. 发明公开

EP0853343A2 Semiconductor memory device having novel layout pattern 失效
标题翻译： Halbleiterspeicherbauteil mit neuartigem布局
公开(公告)号：EP0853343A2
公开(公告)日：1998-07-15
申请号：EP98100032.6
申请日：1998-01-02
申请人： NEC CORPORATION
发明人： Saeki, Takanori
IPC分类号： H01L27/108 , H01L27/105 , H01L27/02
CPC分类号： H01L27/105 , H01L21/761 , H01L27/0218
摘要： A semiconductor memory device laid out to have a deep well of a second conductivity type formed in a semiconductor substrate of a first conductivity type, a cell array well of the first conductivity type formed on said deep well, and an isolation well of the second conductivity type formed around said cell array well to reach said deep well so as to incorporate said cell array well, thereby isolating said cell array well from said semiconductor substrate through said isolation well, wherein a circuit element for driving said cell array is formed in said isolation well.
摘要翻译：一种半导体存储器件，被布置成具有形成在第一导电类型的半导体衬底中的第二导电类型的深阱，形成在所述深阱上的第一导电类型的电池阵列阱以及第二导电类型的隔离阱类型形成在所述单元阵列周围以达到所述深阱以便良好地并入所述单元阵列，从而通过所述隔离阱将所述单元阵列与所述半导体衬底良好隔离，其中用于驱动所述单元阵列的电路元件形成在所述隔离好。

8. 发明公开

EP0848426A1 Integrated circuit device and method of manufacturing same 失效
标题翻译： Integrierte Schaltungsanordnung und Verfahren zum Herstellen derselben
公开(公告)号：EP0848426A1
公开(公告)日：1998-06-17
申请号：EP97309377.6
申请日：1997-11-20
申请人： FUJITSU LIMITED
发明人： Nakamori, Tsutomu
IPC分类号： H01L27/02 , H01L23/528
CPC分类号： H01L23/5286 , H01L27/0207 , H01L27/0218 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims to provide an efficient layout of power supply interconnections in an LSI circuit. An integrated circuit device has a plurality of arrays of cells E on a chip and a plurality of circuit blocks A-D, G larger in scale than the cells and embedded among the arrays of cells. Once the cells and the circuit blocks are placed in a given region of a chip, adjacent circuit blocks A, B, F are grouped. Then a group power supply ring 36, 37 is generated around the grouped circuit blocks and a block power supply ring 38, 39 around other groups or individual circuit blocks C, D. Finally a grid-shaped pattern of internal power supply interconnections 52, 53 is formed on the chip, connecting the group power supply ring and the block power supply ring or rings to the main power supply ring 34, 35. This layout avoids unnecessary power supply wiring around individual blocks if such blocks are adjacent and of compatible sizes.
摘要翻译：本发明旨在提供LSI电路中的电源互连的有效布局。集成电路器件具有芯片上的多个单元阵列E和比单元尺寸更大且嵌入在单元阵列中的多个电路块A-D，G。一旦电池和电路块被放置在芯片的给定区域中，相邻的电路块A，B，F被分组。然后在分组的电路块周围产生组电源环36,37，围绕其他组或单独的电路块C，D围绕块电源环38,39。最后，内部电源互连52,53的网格图案形成在芯片上，将组电源环和块电源环或环连接到主电源环34,35。这种布局避免了如果这些块相邻并且兼容尺寸，则各个块周围的不必要的电源布线。

9. 发明公开

EP0739097A3 MOSFET circuit and CMOS logic circuit using the same 失效
标题翻译： MOSFET Schaltung und ihre Anwendung在einer CMOS Logikschaltung
公开(公告)号：EP0739097A3
公开(公告)日：1998-01-07
申请号：EP96106128.0
申请日：1996-04-18
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： Douseki, Takakuni
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H03K19/0016 , H01L27/0218 , H03K19/00361
摘要： A MOSFET circuit achieving high speed operation and low power consumption for a wide supply voltage range. MOSFET circuits (111 and 112) are connected between a low threshold voltage CMOS circuit (3) and a supply voltage (VDD) and ground, as a power controller for switching power supply in response to sleep/active modes. High threshold voltage MOSFETs (M1 and M3) in the MOSFET circuits (111 and 112) are gate biased by low threshold voltage MOSFETs (M2 and M4), thereby preventing a current from flowing across the backgate terminal and the source terminal.
摘要翻译： MOSFET电路在宽电源电压范围内实现高速运行和低功耗。 MOSFET电路（111和112）连接在低阈值电压CMOS电路（3）和电源电压（VDD）之间，并接地，作为响应于睡眠/活动模式切换电源的功率控制器。 MOSFET电路（111和112）中的高阈值电压MOSFET（M1和M3）由低阈值电压MOSFET（M2和M4）进行栅极偏置，从而防止电流流过背栅极端子和源极端子。

10. 发明授权

EP0477758B1 Semiconductor integrated circuit including P-channel MOS transistors having different threshold voltages 失效
标题翻译：具有不同阈值电压的P沟道MOS晶体管的半导体集成电路
公开(公告)号：EP0477758B1
公开(公告)日：1997-07-30
申请号：EP91115846.7
申请日：1991-09-18
申请人： FUJITSU LIMITED
发明人： Okajima, Yoshinori, c/o Fujitsu Limited
IPC分类号： H01L27/088 , H01L27/02
CPC分类号： H01L27/088 , H01L27/0218

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