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1. 发明授权

EP3096452B1 OPERATIONAL AMPLIFIER CIRCUIT WITH DC OFFSET SUPPRESSION 有权
公开(公告)号：EP3096452B1
公开(公告)日：2018-11-14
申请号：EP15168460.2
申请日：2015-05-20
申请人： ALi Corporation
发明人： Berner, Raphael
IPC分类号： H03F3/45 , H04B1/30
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45659 , H03F3/45748 , H03F3/45946 , H03F3/45973 , H03F2203/45424 , H03F2203/45441 , H03F2203/45521 , H03F2203/45681 , H04B1/30
摘要： An Op-Amp circuit (100), a low pass filter and a RF receiver using the Op-Amp circuit are provided. The Op-Amp circuit includes a first operational amplifier (110) and a feedback circuit (120; 130). The feedback circuit is coupled to an output stage (113) of the first operational amplifier and generates a feedback signal (fb1; fb2) according to a reference voltage (ref) and one of a pair of differential output signals out_p; out_n). The feedback circuit outputs the feedback signal to the output stage (113) to adjust a bias current of the output stage corresponding to the one of the pair of differential output signals, so that a DC voltage level of the one of the pair of differential output signals is close to a voltage level of the reference voltage (ref) and a DC offset of the one of the pair of differential output signals is suppressed.

2. 发明公开

EP3261250A4 AMPLIFICATION CIRCUIT 有权
公开(公告)号：EP3261250A4
公开(公告)日：2018-07-04
申请号：EP16885458
申请日：2016-07-19
申请人： SHENZHEN GOODIX TECH CO LTD
发明人： ZHANG MENGWEN
IPC分类号： H03F3/45 , H03F3/00 , H03F3/187
CPC分类号： H03F1/0205 , H03F1/301 , H03F1/32 , H03F3/005 , H03F3/187 , H03F3/45183 , H03F3/45188 , H03F3/45192 , H03F3/45475 , H03F3/45659 , H03F3/45699 , H03F3/45762 , H03F2200/129 , H03F2200/156 , H03F2200/159 , H03F2200/18 , H03F2200/222 , H03F2200/252 , H03F2200/264 , H03F2200/471 , H03F2200/555 , H03F2203/45008 , H03F2203/45012 , H03F2203/45024 , H03F2203/45028 , H03F2203/45054 , H03F2203/45068 , H03F2203/45082 , H03F2203/45112 , H03F2203/45134 , H03F2203/45136 , H03F2203/45171 , H03F2203/45174 , H03F2203/45182 , H03F2203/45188 , H03F2203/45192 , H03F2203/45208 , H03F2203/45244 , H03F2203/45332 , H03F2203/45421 , H03F2203/45434 , H03F2203/45444 , H03F2203/45512 , H03F2203/45514 , H03F2203/45534 , H03F2203/45544 , H03F2203/45546 , H03F2203/45551 , H03F2203/45586 , H03F2203/45588 , H03F2203/45616 , H03F2203/45632 , H03F2203/45642 , H03F2203/45656 , H03F2203/45674 , H03F2203/45676
摘要： The present application provides an amplifying circuit comprising a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage, the common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage, the common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit provided in the present application can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

3. 发明公开

EP3332477A1 AN ACCURATE SAMPLE LATCH OFFSET COMPENSATION SCHEME 有权
公开(公告)号：EP3332477A1
公开(公告)日：2018-06-13
申请号：EP16748372.6
申请日：2016-07-05
申请人： Qualcomm Incorporated
发明人： CHEN, Minhan , ARCUDIA, Kenneth Luis
IPC分类号： H03F3/45 , H03F3/72 , G11C7/06
CPC分类号： H03K3/356104 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2200/234 , H03F2200/27 , H03F2200/297 , H03F2200/366 , H03F2200/375 , H03F2200/45 , H03F2200/525 , H03F2200/75 , H03F2200/78 , H03F2200/84 , H03F2203/7203
摘要： A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.

4. 发明公开

EP3291446A1 A GALVANIC ISOLATION CIRCUIT, CORRESPONDING SYSTEM AND METHOD 审中-公开
标题翻译：一种电流隔离电路，相应的系统和方法
公开(公告)号：EP3291446A1
公开(公告)日：2018-03-07
申请号：EP17161341.7
申请日：2017-03-16
申请人： STMicroelectronics S.r.l.
发明人： RAGONESE, Egidio , SPINA, Nunzio , PARISI, Alessandro , LOMBARDO, Pierpaolo , GRECO, Nunzio , PALMISANO, Giuseppe
IPC分类号： H03F3/45 , H04L25/02 , H01F19/08
CPC分类号： H04B1/10 , H01F19/04 , H01F2019/085 , H03F3/45183 , H03F3/45632 , H03F2203/45084 , H03F2203/45621 , H03F2203/45642 , H03F2203/45704 , H04L25/02 , H04L25/0266 , H04L25/0272
摘要： A galvanic isolation circuit (GI) includes a differential transformer (20) having primary (21) and secondary (22) windings for transmission of signals over a carrier (DT) between the primary (21) and the secondary (22) windings of the transformer. The primary (21) and secondary (22) windings have a galvanic isolation oxide layer (23) therebetween and include center taps (21a, 22a) providing low-impedance paths for dc and low frequency components of common-mode currents through the differential transformer (20). A pass-band stage (24) coupled to the secondary winding (22) of the transformer (20) is configured for permitting propagation of signals over said carrier through the pass-band amplifier stage (24) while providing rejection of common-mode noise.
摘要翻译：电流隔离电路（GI）包括具有主（21）和副（22）绕组的差动变压器（20），用于通过载波（DT）传输信号在主绕组（21）和次（22）绕组之间变压器。初级绕组（21）和次级绕组（22）在它们之间具有电隔离氧化物层（23）并且包括中心抽头（21a，22a），其为通过差分变压器的共模电流的dc和低频分量提供低阻抗路径（20）。耦合到变压器（20）的次级绕组（22）的通带级（24）被配置为允许信号在所述载波上通过通带放大器级（24）传播，同时提供对共模噪声。

5. 发明公开

EP3214759A4 ULTRA-LOW WORKING VOLTAGE RAIL TO RAIL OPERATIONAL AMPLIFIER AND DIFFERENTIAL INPUT AMPLIFICATION-STAGE CIRCUIT AND OUTPUT-STAGE CIRCUIT THEREOF 无效
公开(公告)号：EP3214759A4
公开(公告)日：2018-02-28
申请号：EP15854770
申请日：2015-10-27
申请人： HUAWEI TECH CO LTD
发明人： TANG YANGYANG , ZHANG CHENXIONG
IPC分类号： H03F3/45 , H03F1/34 , H03F1/38
CPC分类号： H03F1/0205 , H03F1/38 , H03F3/45183 , H03F3/45219 , H03F3/45273 , H03F2200/135 , H03F2200/153 , H03F2200/513 , H03F2200/87 , H03F2203/45028 , H03F2203/45036 , H03F2203/45051 , H03F2203/45054 , H03F2203/45114 , H03F2203/45124 , H03F2203/45134 , H03F2203/45221 , H03F2203/45281 , H03F2203/45288 , H03F2203/45342
摘要： A differential input amplification-stage circuit (100) includes a voltage unit (10), first and second bulk-driven transistors (20, 30), first and second mirror current sources (40, 50), and a differential amplifier unit (60). The voltage unit (10) includes first to third voltage output ends (11, 12, 13). The first voltage output end (11) is connected to the first and the second bulk-driven transistors (20, 30); the first and the second bulk-driven transistors (20, 30) respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents; the differential amplifier unit (60) separately outputs first and second adjustment currents under an action of voltages of the first to the third voltage output ends (11, 12, 13); and the first and the second mirror current sources (40, 50) respectively output first and second predetermined currents (I out+ , I out- ) according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit (100). Therefore, output stability is improved. In addition, an output-stage circuit (200) and an ultra-low working voltage rail-to-rail transportation amplified circuit (300) are further provided.

6. 发明授权

EP2601745B1 INTEGRATED TRANSCEIVERS HAVING MERGED LOW NOISE AND POWER AMPLIFIERS 有权
标题翻译：集成收发器具有合并的低噪声和功率放大器
公开(公告)号：EP2601745B1
公开(公告)日：2017-12-06
申请号：EP11749370.0
申请日：2011-08-02
申请人： OCT Circuit Technologies International Limited
发明人： DE MAAIJER, Luc
IPC分类号： H04B1/48
CPC分类号： H04B1/406 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/45183 , H03F2200/06 , H03F2200/09

7. 发明公开

EP3066756A4 CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
标题翻译： TAKT- UND DATENTREIBER MITERHÖHTERTRANSKONDUKTANZ UNDUNTERDRÜCKTEMGLEICHTAKTBEREICH
公开(公告)号：EP3066756A4
公开(公告)日：2017-07-12
申请号：EP14859633
申请日：2014-11-05
申请人： QUALCOMM INC
发明人： SU WENJUN , YIN GUANGMING , ZHU QUANQING
IPC分类号： H03K5/12 , H03F1/02 , H03F3/21 , H03F3/45 , H03F3/72
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12

8. 发明公开

EP3182587A1 SMALL SIGNAL AMPLIFIER 审中-公开
标题翻译：小信号放大器
公开(公告)号：EP3182587A1
公开(公告)日：2017-06-21
申请号：EP15200499.0
申请日：2015-12-16
申请人： IMEC VZW
发明人： Mora Lopez, Carolina , Mitra, Srinjoy
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F1/26 , A61B5/04001 , H03F1/0261 , H03F3/45179 , H03F3/45183 , H03F3/45188 , H03F3/45192 , H03F3/45475 , H03F2200/171 , H03F2200/261 , H03F2200/513 , H03F2203/45136 , H03F2203/45342 , H03F2203/45526
摘要： An amplifier circuit comprising an input stage comprising a first set of transistors (M5, M6) to which an input signal to be amplified is applied, the transistors of the first set comprising a semiconductor body, and a processing stage comprising a second set of transistors (M13,M14) for processing the signal from the input stage and generating an output signal (Vo). The transistors of the first set have a thicker gate oxide than the transistors of the second set, and are therefore suitable for higher voltage operation, and the first and second sets of transistors are supplied by the same voltage supply (VDD L ) of the amplifier circuit. This reduces the effect of gate leakage currents. The semiconductor body of the first set of transistors is connected to a reference potential (Vbulk) thereby to lower the threshold voltage. This enables the circuit to process a wider range of input signals.
摘要翻译：一种放大器电路，包括：输入级，包括被施加要被放大的输入信号的第一组晶体管（M5，M6），所述第一组晶体管包括半导体本体，以及处理级包括第二组晶体管（M13，M14），用于处理来自输入级的信号并产生输出信号（Vo）。第一组晶体管具有比第二组晶体管更厚的栅极氧化物，因此适用于更高电压操作，并且第一组晶体管和第二组晶体管由放大器电路的相同电压源（VDDL）供应。这减少了门漏电流的影响。第一组晶体管的半导体本体连接到参考电位（Vbulk），从而降低阈值电压。这使电路能够处理更宽范围的输入信号。

9. 发明公开

EP3084976A4 CONFIGURABLE TRANSCEIVER CIRCUIT ARCHITECTURE 有权
标题翻译： KONFIGURIERBARE SENDER /EMPFÄNGER-SCHALTUNGSARCHITEKTUR
公开(公告)号：EP3084976A4
公开(公告)日：2017-05-31
申请号：EP13899443
申请日：2013-12-20
申请人： INTEL CORP
发明人： GAO MIAOBIN , KRAUSE CHRISTINE M , WU HIU-CHIN , CHENG HENGJU
IPC分类号： H04B3/02
CPC分类号： H03F3/45475 , H01L23/48 , H01L2224/48091 , H01L2224/48137 , H01L2924/0002 , H03F1/34 , H03F3/087 , H03F3/45183 , H03F2203/45112 , H03F2203/45206 , H03F2203/45288 , H03F2203/45528 , H03F2203/45641 , H03F2203/45646 , H03F2203/45674 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H04B3/02 , H01L2924/00014 , H01L2924/00
摘要： Techniques and mechanisms for providing signal communication with a configurable transceiver circuit. In an embodiment, an integrated circuit comprises transceiver circuitry including an output stage and current mirror circuitry. The output stage is coupled to receive a differential signal pair and to provide at least one output signal based on the differential signal pair. In another embodiment, configuration logic is operable to select between a first mode and a second mode of the transceiver circuit. The first mode includes the current mirror circuitry being disabled from providing a current signal to the output stage, and a first circuit path being closed to provide voltage to the output stage. The second mode includes the first circuit path being open and the current mirror circuitry being enabled to provide a current signal to the output stage.
摘要翻译：用可配置收发器电路提供信号通信的技术和机制。在一个实施例中，集成电路包括包括输出级和电流镜像电路的收发器电路。输出级被耦合以接收差分信号对并且基于差分信号对提供至少一个输出信号。在另一个实施例中，配置逻辑可操作以在收发器电路的第一模式和第二模式之间进行选择。第一模式包括禁止电流镜像电路向输出级提供电流信号，并且闭合第一电路路径以向输出级提供电压。第二模式包括第一电路路径断开并且电流镜像电路被启用以向输出级提供电流信号。

10. 发明公开

EP2917745A4 INSTRUMENTATION AMPLIFIER WITH RAIL-TO-RAIL INPUT RANGE 审中-公开
标题翻译： INSTRUMENTENVERSTÄRKERMIT RAIL-TO-RAIL-EANGANGSBEREICH
公开(公告)号：EP2917745A4
公开(公告)日：2016-07-06
申请号：EP13852562
申请日：2013-09-25
申请人： SEMTECH CORP
发明人： NYS OLIVIER , KRUMMENACHER FRANCOIS
IPC分类号： H03F3/45 , H03F1/32 , H03F3/30
CPC分类号： H03F1/52 , H03F1/3211 , H03F3/3022 , H03F3/45183 , H03F3/45475 , H03F3/45645 , H03F3/45941 , H03F3/45973 , H03F2200/261 , H03F2203/45082 , H03F2203/45138 , H03F2203/45431 , H03F2203/45434 , H03F2203/45441 , H03F2203/45528

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