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1. 发明公开

EP3316289A3 METHOD TO IMPROVE THE HIGH K QUALITY 有权转让
公开(公告)号：EP3316289A3
公开(公告)日：2018-07-18
申请号：EP17199137.5
申请日：2017-10-30
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： LI, Yong
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/28
CPC分类号： H01L27/0924 , H01L21/28185 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L29/4966 , H01L29/518
摘要： A method of manufacturing a semiconductor device includes providing a substrate structure including PMOS and NMOS regions having respective first and second trenches, a high-k dielectric layer (203) in the first and second trenches, and a first P-type work function adjustment layer (204) on the high-k dielectric layer, sequentially forming first (301) and second (302) protective layers and a mask layer (401) on the substrate structure; removing a portion of the mask layer exposing a portion of the second protective layer (302) on the NMOS region; removing the exposed portion of the second protective layer (302) on the NMOS region exposing a portion of the first protective layer (301) on the NMOS region; removing the mask layer exposing the second protective layer on the PMOS region; removing portions of the first protective layer and first P-type work function adjustment layer on the NMOS region; and removing the second and first protective layers on the PMOS region.

2. 发明公开

EP3123519A4 FIN SCULPTING AND CLADDING DURING REPLACEMENT GATE PROCESS FOR TRANSISTOR CHANNEL APPLICATIONS 无效转让
公开(公告)号：EP3123519A4
公开(公告)日：2017-10-25
申请号：EP14887405
申请日：2014-03-24
申请人： INTEL CORP
发明人： GLASS GLENN A , MURTHY ANAND S , AUBERTINE DANIEL B , JOSHI SUBHASH M
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/02532 , H01L21/3065 , H01L21/823431 , H01L21/823437 , H01L21/823821 , H01L21/823828 , H01L27/0886 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).

3. 发明公开

EP3179507A3 HIGH-K METAL GATE TRANSISTOR STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：高K金属栅极晶体管结构及其制造方法
公开(公告)号：EP3179507A3
公开(公告)日：2017-08-02
申请号：EP16199544.4
申请日：2016-11-18
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： LI, Yong
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51 , H01L21/336 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/28088 , H01L21/28185 , H01L21/31051 , H01L21/32115 , H01L21/324 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L27/092 , H01L29/0649 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/785
摘要： The present invention provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.
摘要翻译：本发明提供HKMG晶体管结构及其制造方法。一种示例性方法包括提供具有第一区域和第二区域的基础衬底; 形成在所述第一区域中具有第一开口并且在所述第二区域中具有第二开口的电介质层; 在所述第一开口的侧表面上以及所述基底基板的所述第一开口中和所述第二开口的侧表面上以及所述基底基板的所述第二开口中的一部分上形成栅极电介质层; 在第一开口中填充牺牲层; 在第二开口中形成第二功函数层，并在第二功函数层上形成第二栅电极层; 去除牺牲层; 以及在第一开口中形成第一功函数层，并在第一功函数层上形成第一栅电极层。

4. 发明公开

EP3190618A1 AN ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：一种静电放电保护结构及其制造方法
公开(公告)号：EP3190618A1
公开(公告)日：2017-07-12
申请号：EP16207262.3
申请日：2016-12-29
申请人： Semiconductor Manufacturing International Corporation (Beijing) , Semiconductor Manufacturing International Corporation (Shanghai)
发明人： ZHOU, Fei
IPC分类号： H01L27/02 , H01L29/861
CPC分类号： H01L27/0255 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L27/0296 , H01L27/0924 , H01L29/0649 , H01L29/0657 , H01L29/0692 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/7848 , H01L29/861
摘要： A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.
摘要翻译：提供了一种用于制造静电放电（ESD）保护结构的方法。该方法包括形成具有第一区域和第二区域的基板，其中第一区域和第二区域具有预设距离; 在衬底中形成阱区; 在所述第一区域中的所述衬底中和所述第二区域中的所述衬底中形成第一鳍部分; 形成支撑栅极结构，其中所述支撑栅极结构包括与所述第一鳍部分交叉的第一支撑栅极和与所述第二鳍部分交叉的第二支撑栅极; 在阱区上形成电介质层; 以及在介电层中形成导电结构，其中导电结构包括连接到第一鳍状部分的第一导电结构和连接到第二鳍状部分的第二导电结构。

5. 发明公开

EP3123519A1 FIN SCULPTING AND CLADDING DURING REPLACEMENT GATE PROCESS FOR TRANSISTOR CHANNEL APPLICATIONS 无效转让
标题翻译： RIPPENFORMUNG UND-EXKLEIDUNGWÄHRENDEINES ERSATZGATEPROZESSESFÜRTRANSISTORKANALANWENDUNGEN
公开(公告)号：EP3123519A1
公开(公告)日：2017-02-01
申请号：EP14887405.0
申请日：2014-03-24
申请人： Intel Corporation
发明人： GLASS, Glenn A. , MURTHY, Anand S. , AUBERTINE, Daniel B. , JOSHI, Subhash M.
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/02532 , H01L21/3065 , H01L21/823431 , H01L21/823437 , H01L21/823821 , H01L21/823828 , H01L27/0886 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).
摘要翻译：公开了用于在替换栅极处理（例如，对于晶体管通道应用）中在半导体衬底上的鳍的沟道区进行雕刻和包层的技术。在更换闸门处理中使用的虚拟门被去除之后，当翅片的通道区域再曝光时，可以进行雕刻和包层。雕刻包括在鳍片的再曝光的通道区域上进行修剪蚀刻以使散热片的宽度变窄（例如，2-6nm）。然后可以将包括锗（Ge）或硅锗（SiGe）的包覆层沉积在修整的翅片上，留下翅片的源极/漏极区域不受影响。雕刻和包层可以在原位或无空气破裂的情况下进行，以提高修剪的翅片的质量（例如，与非原位工艺相比）。

6. 发明授权

EP2206146B1 METHODS, STRUCTURES AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS USED IN INTEGRATED CIRCUITS 有权
标题翻译：方法，集成电路结构和设计中使用的自调心本地连接元件
公开(公告)号：EP2206146B1
公开(公告)日：2017-01-18
申请号：EP08842026.0
申请日：2008-10-20
申请人： Tela Innovations, Inc.
发明人： SMAYLING, Michael, C. , BECKER, Scott, T.
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/285
CPC分类号： H01L27/092 , G03F1/14 , G06F17/5077 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates (74) are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions (180). The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers (230). The method also includes designing a local interconnect layer (196) between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions (184) of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

7. 发明公开

EP2761662A4 TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS 有权转让
标题翻译：钨盖茨非平面TRANSISTORS
公开(公告)号：EP2761662A4
公开(公告)日：2015-08-05
申请号：EP11873428
申请日：2011-09-30
申请人： INTEL CORP
发明人： PRADHAN SAMEER S , BERGSTROM DANIEL B , CHUN JIN-SUNG , CHIU JULIA
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L29/49
CPC分类号： H01L21/823828 , H01L21/76897 , H01L21/823857 , H01L29/41791 , H01L29/495 , H01L29/51 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L2029/7858

8. 发明授权

EP2592649B1 Method for forming self-aligning local interconnects in integrated circuits 有权
标题翻译：在集成电路制造自对准局部互连方法
公开(公告)号：EP2592649B1
公开(公告)日：2015-04-29
申请号：EP13154842.2
申请日：2008-10-20
申请人： Tela Innovations, Inc.
发明人： Smayling, Michael C , Becker, Scott T
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/768 , H01L21/285 , H01L27/088 , G06F17/50 , G03F1/00
CPC分类号： H01L27/092 , G03F1/14 , G06F17/5077 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates (74) are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions (180). The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers (230). The method also includes designing a local interconnect layer (196) between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions (184) of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.

9. 发明公开

EP2234150A3 Semiconductor device and production method therefor 审中-公开
公开(公告)号：EP2234150A3
公开(公告)日：2012-04-04
申请号：EP10003151.7
申请日：2010-03-24
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Masuoka, Fujio , Nakamura, Hiroki
IPC分类号： H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/786
CPC分类号： H01L27/092 , H01L21/823828 , H01L21/823878 , H01L21/823885 , H01L21/84 , H01L27/1203 , H01L29/78642
摘要： It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer.

10. 发明公开

EP2299484A2 Semiconductor device comprising surrounding gate transistors. 有权转让
标题翻译： Halbleiterbauelement mit Transistoren mitumschließendemGate
公开(公告)号：EP2299484A2
公开(公告)日：2011-03-23
申请号：EP10009579.3
申请日：2010-09-14
申请人： Unisantis Electronics (Japan) Ltd.
发明人： Masuoka, Fujo , Nakamura, Hiroki
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092
CPC分类号： H01L21/823885 , H01L21/823828 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L29/78642
摘要： The semiconductor device is provided with SRAM using an inverter circuit having: a first gate insulating film 192 surrounding the periphery of the first island-shaped silicon layer 109, a first gate electrode 183 surrounding the periphery of the first gate insulating film 192, a second gate insulating film 192 surrounding the periphery of the first gate electrode, a first columnar silicon layer 133 surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of the first conductivity type 149 formed in the upper part of the first island-shaped silicon layer, a second lower part high concentration semiconductor layer of the first conductivity type 153 formed in the lower part of the first island-shaped silicon layer, a first upper part high concentration semiconductor layer of the second conductivity type 161 formed in the upper part of the first columnar silicon layer, and a second lower part high concentration semiconductor layer of the second conductivity type 163 formed in the lower part of the first columnar silicon layer.
摘要翻译：半导体器件具有使用逆变器电路的SRAM，该逆变器电路具有：围绕第一岛状硅层109周围的第一栅极绝缘膜192，围绕第一栅极绝缘膜192周边的第一栅电极183，栅绝缘膜192，围绕第一栅电极的周围的第一柱状硅层133，围绕第二栅极绝缘膜的周围的第一柱状硅层133，形成在第一栅极绝缘膜的上部的第一导电类型的第一上部高浓度半导体层第一岛状硅层，形成在第一岛状硅层的下部的第一导电类型153的第二下部高浓度半导体层，形成第二导电型161的第一上部高浓度半导体层在第一柱状硅层的上部和第二下部高浓度半导体1a 形成在第一柱状硅层的下部的第二导电类型163的yer。

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