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1. 发明授权

EP2248178B1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP2248178B1
公开(公告)日：2018-10-10
申请号：EP09706248.3
申请日：2009-01-14
申请人： Kabushiki Kaisha Toshiba
发明人： SUZUKI, Takuma , KONO, Hiroshi , SHINOHE, Takashi
IPC分类号： H01L29/78 , H01L29/739 , H01L29/417 , H01L29/36 , H01L21/336 , H01L21/04 , H01L29/423 , H01L29/45 , H01L29/16
CPC分类号： H01L29/7802 , H01L21/0465 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/45 , H01L29/66068 , H01L29/7395 , H01L29/7816
摘要： According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.

2. 发明公开

EP3227913A4 THIN FILM TRANSISTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS 审中-公开
公开(公告)号：EP3227913A4
公开(公告)日：2018-07-25
申请号：EP15849828
申请日：2015-08-14
申请人： BOE TECHNOLOGY GROUP CO LTD , CHONGQING BOE OPTOELECTRONICS CO LTD
发明人： WANG WU , QIU HAIJUN , SHANG FEI , WANG GUOLEI
IPC分类号： H01L29/417 , H01L21/336 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L27/1288 , H01L21/0274 , H01L21/441 , H01L21/47573 , H01L21/47635 , H01L27/1225 , H01L29/41725 , H01L29/41733 , H01L29/45 , H01L29/66969 , H01L29/78615 , H01L29/78618 , H01L29/7869
摘要： Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

3. 发明授权

EP1970945B1 Method of manufacturing a silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：EP1970945B1
公开(公告)日：2018-05-09
申请号：EP08152760.8
申请日：2008-03-14
申请人： Nissan Motor Co., Ltd.
发明人： TANIMOTO, Satoshi
IPC分类号： H01L29/66 , H01L21/04 , H01L29/78 , H01L29/45 , H01L29/417 , H01L29/94 , H01L29/739
CPC分类号： H01L29/7802 , H01L21/0485 , H01L21/049 , H01L29/41766 , H01L29/45 , H01L29/6606 , H01L29/66068 , H01L29/7395 , H01L29/94
摘要： A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, advantageously 15 nm or less.

4. 发明公开

EP3314635A1 METHOD TO FORM OHMIC CONTACTS TO SEMICONDUCTORS USING QUANTIZED METALS 审中-公开
标题翻译：用量化金属形成欧姆接触到半导体的方法
公开(公告)号：EP3314635A1
公开(公告)日：2018-05-02
申请号：EP15897299.2
申请日：2015-06-27
申请人： INTEL Corporation
发明人： CHU-KUNG, Benjamin , LE, Van H. , RIOS, Rafael , DEWEY, Gilbert , CLENDENNING, Scott B. , KAVALIEROS, Jack T.
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/28
CPC分类号： H01L29/45 , H01L21/28556 , H01L21/28568 , H01L21/76802 , H01L21/76883 , H01L23/49827 , H01L23/49838 , H01L29/0847 , H01L29/41783 , H01L29/66568 , H01L29/78
摘要： An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

5. 发明公开

EP3179518A4 THIN-FILM TRANSISTOR AND PREPARATION METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY DEVICE 审中-公开
公开(公告)号：EP3179518A4
公开(公告)日：2018-03-28
申请号：EP16822102
申请日：2016-02-03
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： HUANG YONGCHAO
IPC分类号： H01L29/45 , G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L21/02 , H01L21/04 , H01L27/12 , H01L27/32 , H01L29/16 , H01L29/167 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/786 , H01L51/52
CPC分类号： H01L29/4908 , G02F1/134309 , G02F1/13439 , G02F1/1362 , G02F1/136286 , G02F1/1368 , G02F2201/121 , G02F2201/123 , G02F2202/10 , H01L21/02527 , H01L21/0259 , H01L21/0262 , H01L21/043 , H01L21/044 , H01L27/124 , H01L27/3262 , H01L29/1606 , H01L29/167 , H01L29/408 , H01L29/41733 , H01L29/42384 , H01L29/45 , H01L29/458 , H01L29/66045 , H01L29/78606 , H01L29/78684 , H01L51/5206
摘要： The present disclosure provides a thin film transistor, a method for producing the same, an array substrate and a display apparatus. An electrode of the thin film transistor is made of Cu or Cu alloy, and an anti-oxidization layer is used to prevent oxidization of Cu. The thin film transistor includes a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode and a drain electrode provided on a base substrate, wherein the gate electrode and/or the drain and source electrodes is/are made of Cu or Cu alloy. The thin film transistor further includes an anti-oxidization layer made of a topological insulator material, the anti-oxidization layer being provided above and in contact with the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy.

6. 发明公开

EP3128553A4 ARRAY SUBSTRATE AND METHOD FOR FABRICATION AND DISPLAY DEVICE THEREOF 审中-公开
公开(公告)号：EP3128553A4
公开(公告)日：2018-01-24
申请号：EP14861185
申请日：2014-07-11
申请人： BOE TECHNOLOGY GROUP CO LTD
发明人： CHOI SEUNGJIN , KIM HEECHEOL , SONG YOUNGSUK , YOO SEONGYEOL
IPC分类号： G02F1/1362 , G02F1/1343 , H01L27/12
CPC分类号： G02F1/134309 , G02F1/133345 , G02F1/134363 , G02F1/13439 , G02F1/136227 , G02F1/136286 , G02F2001/134318 , G02F2001/134372 , G02F2001/136295 , G02F2201/121 , G02F2201/123 , H01L21/324 , H01L21/76802 , H01L21/77 , H01L27/12 , H01L27/124 , H01L27/1259 , H01L29/45
摘要： The embodiments of the invention disclose an array substrate, a manufacturing method thereof and a display device. Due to the fact that the surfaces of a source electrode, a drain electrode and a data line which are arranged on the same layer are provided with an oxide film which is formed after annealing treatment is conducted on the source electrode, the drain electrode and the data line, in the process that the pattern of a pixel electrode is formed on the source electrode, the drain electrode and the data line by the adoption of a composition technology, the oxide film can protect the source electrode and the data line under the oxide film from being corroded by an etching agent when the pattern of the pixel electrode is formed by etching, and the display quality of a display panel will not be affected; meanwhile, a connecting portion enables the drain electrode to be electrically connected with the pixel electrode through a first via hole arranged over the drain electrode and penetrating through the oxide film, therefore the normal display function of the display panel can be ensured.

7. 发明公开

EP3121840A4 THIN-FILM TRANSISTOR AND PREPARATION METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY PANEL 审中-公开
公开(公告)号：EP3121840A4
公开(公告)日：2017-11-22
申请号：EP15882903
申请日：2015-10-09
申请人： BOE TECHNOLOGY GROUP CO LTD , UNIV SOUTH CHINA TECH
发明人： YUAN GUANGCAI , YAN LIANGCHEN , XU XIAOGUANG , WANG LEI , PENG JUNBIAO , LAN LINFENG
IPC分类号： H01L29/786 , H01L21/3213 , H01L21/324 , H01L21/34 , H01L27/12 , H01L29/10 , H01L29/45 , H01L29/66
CPC分类号： H01L27/1288 , H01L21/32133 , H01L21/32139 , H01L21/324 , H01L21/34 , H01L27/1248 , H01L29/1079 , H01L29/41733 , H01L29/42384 , H01L29/45 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/78618 , H01L29/7869
摘要： This invention discloses a thin film transistor and the preparation method thereof, an array substrate, and a display panel, so as to solve the problem that the active layer is prone to be corroded when a metal oxide thin film transistor is produced by a back channel etching process. The preparation method comprises: forming a gate electrode metal thin film on a base substrate, and allowing the gate electrode metal thin film to form a gate electrode metal layer comprising a gate electrode by a patterning process; forming a gate electrode insulating layer on the gate electrode metal layer; forming an active layer on the gate electrode insulating layer; preparing a metal nanoparticle layer on the active layer, said metal nanoparticle layer being used as an etching protection layer; forming a source and drain electrode metal thin film on the base substrate on which the above processes are finished, and allowing the source and drain electrode metal thin film to form a source and drain electrode metal layer comprising a source electrode and a drain electrode by a patterning process, wherein the source electrode and the drain electrode cover a part of the metal nanoparticle layer; removing or oxidizing the part of the metal nanoparticle layer which is not covered by the source electrode and the drain electrode in an oxygen-containing atmosphere; and forming a passivation layer on the source and drain electrode metal layer.

8. 发明公开

EP3243220A1 SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING METAL GATES AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有金属门的分裂门非易失性闪存单元及其制造方法
公开(公告)号：EP3243220A1
公开(公告)日：2017-11-15
申请号：EP15819943.0
申请日：2015-12-08
申请人： Silicon Storage Technology Inc.
发明人： CHEN, Chun-ming , WU, Man-tang , YANG, Jeng-wei , SU, Chien-sheng
IPC分类号： H01L29/423 , H01L29/66 , H01L29/788 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/45 , H01L29/4916 , H01L29/495 , H01L29/511 , H01L29/517 , H01L29/66825 , H01L29/788 , H01L29/7881
摘要： A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

9. 发明公开

EP3231008A1 METHOD FOR MANUFACTURING A WIDE BANDGAP JUNCTION BARRIER SCHOTTKY DIODE 审中-公开
标题翻译：制造宽带结电阻肖特基二极管的方法
公开(公告)号：EP3231008A1
公开(公告)日：2017-10-18
申请号：EP15794507.2
申请日：2015-11-04
申请人： ABB Schweiz AG
发明人： MINAMISAWA, Renato , RAHIMO, Munaf
IPC分类号： H01L21/329 , H01L29/872 , H01L21/28 , H01L29/06 , H01L29/40 , H01L29/45 , H01L29/47 , H01L29/24 , H01L29/20
CPC分类号： H01L21/0485 , H01L21/048 , H01L21/0495 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/401 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66212 , H01L29/872
摘要： A method for manufacturing a wide bandgap junction barrier Schottky diode having an anode side and a cathode side is provided, wherein an (n+) doped cathode layer is arranged on the cathode side, at least on p doped anode layer is arranged on the anode side, an (n−) doped drift layer is arranged between the cathode layer and the at least one anode layer, which drift layer extends to the anode side, wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate, b) creating the drift layer on the cathode layer, c) creating the at least one anode layer on the drift layer, d) applying a first metal layer on the anode side on top of the drift layer for forming a Schottky contact, characterized in, that e) creating a second metal layer on top of at least one anode layer, wherein after having created the first and the second metal layer, a metal layer on top of the at least one anode layer has a second thickness and a metal layer on top of the drift layer has a first thickness, wherein the second thickness is smaller than the first thickness, f) then performing a first heating step at a first temperature, by which due the second thickness being smaller than the first thickness an ohmic contact is formed at the interface between the second metal layer and the at least one anode layer, wherein performing the first heating step such that a temperature below the first metal layer is kept below a temperature for forming an ohmic contact.
摘要翻译：提供了一种制造具有阳极侧（10）和阴极侧（15）的宽带隙结型势垒肖特基二极管（1）的方法，其中在阴极侧（15）上布置（n +）掺杂阴极层（2），在阳极侧（10）上布置至少一个p掺杂阳极层（3），在阴极层（2）和至少一个阳极层（3）之间布置（n-）掺杂漂移层（4）），所述漂移层（4）延伸到阳极侧（10），其中执行以下制造步骤：a）提供（n +）掺杂的宽带隙衬底（100），b）（2），c）在漂移层（4）上形成至少一个阳极层（3），d）在漂移层（4），用于形成肖特基接触（55），其特征在于，e）在至少一个阳极层（3）的顶部上形成第二金属层（6），其中在形成第一和第二金属层 5，6），一个见面在所述至少一个阳极层（3）的顶部上具有第二厚度（64）并且在所述漂移层（4）的顶部上的金属层具有第一厚度（54），其中所述第二厚度（64）是 f）然后在第一温度下执行第一加热步骤（63），由此第二厚度（64）小于第一厚度（54），因此欧姆接触（65）是小于第一厚度形成在所述第二金属层（6）和所述至少一个阳极层（3）之间的界面处，其中执行所述第一加热步骤（63），使得所述第一金属层（5）下方的温度保持低于形成欧姆接触。

10. 发明公开

EP2743984A3 ARRAY SUBSTRATE AND THE METHOD FOR MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE 审中-公开
标题翻译：阵列基板及其制造方法及液晶显示装置
公开(公告)号：EP2743984A3
公开(公告)日：2017-09-13
申请号：EP13196720.0
申请日：2013-12-11
申请人： BOE Technology Group Co., Ltd.
发明人： Liu, Xiang
IPC分类号： H01L27/12 , H01L29/786 , H01L29/45 , H01L29/66 , G02F1/1368
CPC分类号： G02F1/1368 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/127 , H01L29/45 , H01L29/66969 , H01L29/7869
摘要： The present invention provides an array substrate, the method for manufacturing the same, and a liquid crystal display device, wherein the array substrate comprises: a gate electrode, a gate insulating layer, a barrier layer pattern and an active semiconductor layer pattern formed by metal oxide semiconductor which are located on the gate insulating layer, a semiconductor protecting layer which covers the barrier layer pattern and the active semiconductor layer pattern, and has via holes at positions corresponding to the barrier layer pattern and the active semiconductor layer pattern; a data wire, a source electrode and a drain electrode formed by metal Cu, which are located at via holes. Metal Cu is used to form the data wire, the source electrode and the drain electrode, and the metal oxide semiconductor is used as the barrier layer for the metal Cu, and as a result, the diffusion of metal Cu into the layers such as the gate insulating layer etc., is prevented in the manufacturing process of TFT.
摘要翻译：本发明提供了一种阵列基板及其制造方法和液晶显示装置，所述阵列基板包括：栅电极，栅绝缘层，势垒层图形以及由金属形成的有源半导体层图形位于所述栅极绝缘层上的氧化物半导体;覆盖所述势垒层图案和所述有源半导体层图案的半导体保护层;以及在与所述势垒层图案和所述有源半导体层图案相对应的位置处具有过孔; 数据线，由金属Cu形成的源电极和漏电极，位于通孔处。金属Cu被用于形成数据线，源电极和漏电极，并且金属氧化物半导体被用作用于金属Cu的阻挡层，结果，金属Cu扩散到诸如在TFT的制造过程中防止了栅极绝缘层等。

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