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1. 发明公开

EP4325781A1 SIGNAL REFLECTION MITIGATION SYSTEMS 审中-实审
公开(公告)号：EP4325781A1
公开(公告)日：2024-02-21
申请号：EP23191175.1
申请日：2023-08-11
申请人： Hamilton Sundstrand Corporation
发明人： BLANKENSHIP, Dale
IPC分类号： H04L25/02 , H05K1/02 , H05K1/11 , H05K1/18 , H03K19/0175
摘要： A circuit can include a closed loop bus line (101) having a plurality of connections. The circuit can include a plurality of integrated circuits (103, 103b, 103c, 103d, 105) disposed on the close loop bus line at a respective connection of the plurality of connections. One or more of the integrated circuits can be configured to drive a signal on the closed loop bus line. The closed loop bus line can be configured to prevent signal reflection. For example, in certain embodiments, there are no termination resistors at any of the terminations to reduce size, weight, and/or part count of the circuit.

2. 发明授权

EP3652860B1 PEGELWANDLER UND EIN VERFAHREN ZUM WANDELN VON PEGELWERTEN IN FAHRZEUGSTEUERGERÄTEN 有权
公开(公告)号：EP3652860B1
公开(公告)日：2023-12-27
申请号：EP18739455.6
申请日：2018-06-12
发明人： FEUCHT, Thomas
IPC分类号： H03K19/082 , H03K19/094 , H03K19/0175 , H03K5/003 , H03K19/0185

3. 发明公开

EP4152014A1 CIRCUITS AND METHODS FOR SUPPLY VOLTAGE DETECTION AND TIMING MONITORING 审中-实审
公开(公告)号：EP4152014A1
公开(公告)日：2023-03-22
申请号：EP22181831.3
申请日：2022-06-29
申请人： INTEL Corporation
发明人： KHELLAH, Muhammad , TSCHANZ, James , KOEBERL, Patrick , TOKUNAGA, Carlos , VANGAL, Sriram R. , PATEL, Pratik , BANG, Suyoung , BAUTISTA GABRIEL, Miguel Mario
IPC分类号： G01R19/165 , G06F21/75 , H03K19/0175 , H03K19/0185 , H03K19/17768 , H03K19/1778 , H03K19/17784
摘要： A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

4. 发明公开

EP4131783A1 OUTPUT DRIVING CIRCUIT AND MEMORY 无效
公开(公告)号：EP4131783A1
公开(公告)日：2023-02-08
申请号：EP21773281.7
申请日：2021-02-08
申请人： Changxin Memory Technologies, Inc.
发明人： XU, Yan
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/017
摘要： The present application provides an output driving circuit and a memory. The output driving circuit includes: a signal input terminal inputting a positive input signal and a negative input signal complementary to each other; a pull-up output unit connected to the signal input terminal, the positive input signal acting as an input signal of the pull-up output unit; a pull-down output unit connected to the signal input terminal, the negative input signal acting as an input signal of the pull-down output unit; at least one compensation unit connected in parallel with the pull-up output unit or the pull-down output unit; at least one pulse signal generation circuit having an input terminal connected to the signal input terminal, and generating a pulse signal based on the positive input signal or the negative input signal, the pulse signal acting as a control signal of the compensation unit; and a signal output terminal connected to an output terminal of the pull-up output unit, an output terminal of the pull-down output unit and an output terminal of the compensation unit, and outputting an output signal. The output driving circuit according to the present application can increase a slew rate of the output signal of the output terminal, thereby improving the performance of the memory.

5. 发明授权

EP3688873B1 GALVANIC ISOLATED DEVICE AND CORRESPONDING SYSTEM 有权
公开(公告)号：EP3688873B1
公开(公告)日：2022-08-17
申请号：EP18773474.4
申请日：2018-09-28
发明人： MARCHAND, Philippe , FOUQUE, Claude , SALOU, Frédérique
IPC分类号： H03K19/0175 , H04B10/80

6. 发明授权

EP3712734B1 SAFE-INPUT DYNAMIC SAMPLING CIRCUIT 有权
公开(公告)号：EP3712734B1
公开(公告)日：2022-08-03
申请号：EP18875763.7
申请日：2018-05-09
发明人： ZHU, Lixiong , WANG, Hailong , NIU, Jianhua , ZHOU, Wei , HE, Longlong , HUANG, Binbin , ZHOU, Rong , MENG, Qingyao
IPC分类号： G05B19/042 , H03K19/0175

7. 发明公开

EP4030306A1 IDENTIFICATION/COMMUNICATION INTERFACE BETWEEN CONSUMER ELECTRONIC DEVICES AND ACCESSORY DEVICES 审中-实审
公开(公告)号：EP4030306A1
公开(公告)日：2022-07-20
申请号：EP22151454.0
申请日：2022-01-13
申请人： Google LLC
发明人： ZHANG, Hoaxing , HO, Dietich Shing-Quan , LEE, Hung-Yang , SAPERSTEIN, William
IPC分类号： G06F13/42 , G01R19/00 , G01R19/165 , G01R19/257 , G06F13/14 , G06F13/20 , G06F13/38 , G06F13/40 , G06N3/063 , H03K19/0175 , H04Q1/20 , H04Q1/24
摘要： An accessory interface for an electronic host device includes a digital communication bus including a plurality of communication lines configured to pass data between the electronic host device and an electronic accessory device. The accessory interface further includes detection circuitry selectively coupled to the plurality of communication lines via a multiplexer and configured to detect analog voltage levels across the plurality of communication lines, determine a device type of the electronic accessory device based on the detected analog voltage levels, and control the multiplexer to couple the plurality of communication lines to a host processor of the electronic host device upon determining the device type of the electronic accessory device. The host processor is configured to receive the device type of the electronic accessory device and transmit data via the plurality of communication lines to the electronic accessory device in accordance with the device type of the electronic accessory device.

8. 发明授权

EP3388793B1 ELEKTRONISCHE BAUGRUPPE FÜR PERIPHERIEGERÄTE EINES FLUGGERÄTS 有权
公开(公告)号：EP3388793B1
公开(公告)日：2022-06-22
申请号：EP18162788.6
申请日：2018-03-20
发明人： Fink, Cornelius , Immler, Thomas
IPC分类号： G01D21/00 , G06F13/40 , H03K19/0175 , G05B19/042

9. 发明公开

EP3993268A1 CONFIGURABLE INPUT/OUTPUT DEVICE AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：EP3993268A1
公开(公告)日：2022-05-04
申请号：EP20213661.0
申请日：2020-12-14
申请人： Moxa Inc.
发明人： WU, Kun-Nan
IPC分类号： H03K19/0175
摘要： A configurable input/output device includes a plurality of input/output terminals, a routing module, and a first universal input/output channel. The input/output terminals are connected a plurality of field devices. The input/output terminals receive a plurality of input signals from the field devices, and output a plurality of output signals to the field devices. At least two of the input signals are different, at least two of the output signals are different, and at least two the field devices are different. The routing module is connected to the input/output terminals. The first universal input/output channel is connected to the routing module. The routing module controls connections between the first universal input/output channel and the input/output terminals. The routing module also controls the transceiving sequence for the input signals and the output signals.

10. 发明公开

EP3973633A1 TUNABLE DRIVER 审中-实审
公开(公告)号：EP3973633A1
公开(公告)日：2022-03-30
申请号：EP20731322.2
申请日：2020-05-19
申请人： Cisco Technology, Inc.
发明人： APPEL, Craig S. , METZ, Peter C. , PAMPANIN, Joseph V. , SUNDER, Sanjay
IPC分类号： H03K19/003 , H03K19/0175

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