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1. 发明公开

EP4354736A3 CONTINUOUS DIFFUSION CONFIGURABLE STANDARD CELL ARCHITECTURE 审中-实审
公开(公告)号：EP4354736A3
公开(公告)日：2024-08-07
申请号：EP24152929.6
申请日：2016-01-13
申请人： QUALCOMM Incorporated
发明人： SAHU, Satyanarayana , PUCKETT, Joshua Lance , KWON, Ohsang , GOODALL III, William James , BOWERS, Benjamin John
IPC分类号： H01L27/118 , H03K19/0175 , H03K19/17728 , H03K19/17736 , H03K19/20 , H01L27/02
CPC分类号： H01L27/0207 , H03K19/017581 , H03K19/20 , H03K19/17728 , H03K19/17736 , H01L27/11807 , H01L2027/1187420130101
摘要： At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

2. 发明公开

EP4300826A1 INTERFACE CIRCUIT AND CONTROL METHOD THEREOF, CHIP, TERMINAL DEVICE 审中-实审
公开(公告)号：EP4300826A1
公开(公告)日：2024-01-03
申请号：EP21930774.1
申请日：2021-03-17
申请人： Huawei Technologies Co., Ltd.
发明人： QIAN, Zhaohua , WANG, Jingjing , CHEN, Yanqin , KE, Jiandong
IPC分类号： H03K19/0175
摘要： An interface circuit, a method for controlling the interface circuit, a chip, and a terminal device are provided, to avoid a problem of current backflow. The interface circuit includes a first PMOS transistor, an input signal control circuit (10), a bias circuit (20), a signal input end, and an input/output end. The bias circuit (20) includes a substrate bias voltage generation end and a bias voltage generation end. The bias circuit (20) is coupled to a high-level power supply end, the input/output end, and a ground end. The input signal control circuit (10) is connected to the signal input end, the bias voltage generation end, and a gate of the first PMOS transistor; a first electrode of the first PMOS transistor is connected to the high-level power supply end, and a second electrode of the first PMOS transistor is connected to the input/output end; the substrate bias voltage generation end is connected to a substrate of the first PMOS transistor; the input signal control circuit (10) is configured to transmit an electrical signal of the signal input end or an electrical signal of the bias voltage generation end to the gate of the first PMOS transistor; and the bias circuit (20) is configured to perform connection and conduction between the high-level power supply end or the input/output end and the substrate bias voltage generation end.

3. 发明授权

EP3516771B1 STACKED COLUMNAR INTEGRATED CIRCUITS 有权
公开(公告)号：EP3516771B1
公开(公告)日：2024-01-03
申请号：EP17765315.1
申请日：2017-08-29
发明人： WU, Ephrem, C.
IPC分类号： H03K19/0175 , H03K19/177

4. 发明公开

EP4295485A1 PEGELWANDLER 审中-实审
公开(公告)号：EP4295485A1
公开(公告)日：2023-12-27
申请号：EP22709195.6
申请日：2022-01-27
申请人： Endress+Hauser SE+Co. KG
发明人： STRITTMATTER, Christian , GERWIG, Simon , SCHÄUBLE, Harald
IPC分类号： H03K5/02 , H03K19/0175

5. 发明公开

EP4254011A3 LICHTMODUL UND LIDAR-VORRICHTUNG MIT MINDESTENS EINEM DERARTIGEN LICHTMODUL 审中-实审
公开(公告)号：EP4254011A3
公开(公告)日：2023-11-01
申请号：EP23187887.7
申请日：2021-01-07
申请人： Elmos Semiconductor SE
发明人： SROWIG, Andre , FINKELDEY, Fabian
IPC分类号： G01S7/481 , H01S5/0233 , H01S5/026 , H01S5/042 , G01S17/14 , G01S7/484 , G01S17/10 , G01S17/42 , G01S17/89 , H01S5/40 , H03K19/0175
摘要： Das Lichtmodul weist einen Träger (TR) mit Schaltungs-Die auf, wobei auf der Oberseite (TRO) des Trägers (TR) mittels Die-zu-Die-Bondings ein Leuchtdioden-Die (D1D) und ein diesem zugeordnetes Ladungsspeicherbauteil (LSBT) elektrisch mit den Leitungspfad-Anschlussfeldern (TAF1, TAF2) eines Transistors (T dis ) verbunden sind. Die elektrische Verbindung zwischen den beiden Dies und dem Leitungspfad (LPF) des Transistors (T dis ) ist so kurz wie möglich. Oberseitig der beiden Dies befinden sich jeweils ein Anschlussfeld (DAF2, LAF2), die mit einem kurzen Bonddraht (BD1) miteinander verbunden sind. Dieser Entladeschaltkreis ist hinsichtlich der Reduktion parasitärer Induktivitäten und ohmschen Widerstände optimiert. Das Ladungsspeicherbauteil (LSBT) wird mittels einer Aufladeschaltung (B1) aufgeladen, die über einen zweiten Bonddraht (BD2) mit dem Ladungsspeicherbauteil (LSBT) elektrisch verbunden ist. Der zweite Bonddraht (BD2) ist länger als der erste Bonddraht (BD1). Das Lichtmodul kann Teil einer LIDAR-Vorrichtung sein, die ein spezielles Optiksystem aufweisen kann. Die Treiberschaltung für den Transistor (T dis ) kann ebenfalls in besonderer Weise ausgeführt sein.

6. 发明公开

EP4243287A2 LOW POWER CYCLE TO CYCLE BIT TRANSFER IN GATE DRIVERS 有权
公开(公告)号：EP4243287A2
公开(公告)日：2023-09-13
申请号：EP23182216.4
申请日：2020-01-23
申请人： Infineon Technologies Austria AG
发明人： GRASSO, Massimo , MORINI, Sergio , PAGANINI, Amedeo , RESPIGO, Davide
IPC分类号： H03K17/18 , H03K19/0175
摘要： A gate driver includes a high-side region that operates in a first voltage domain, a low-side region that operations in a second voltage domain lower than the first voltage domain, a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain, a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, where each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.

7. 发明公开

EP4203319A1 INTERLEAVED SIGNAL GENERATING CIRCUIT 审中-实审
公开(公告)号：EP4203319A1
公开(公告)日：2023-06-28
申请号：EP21929821.3
申请日：2021-08-11
申请人： Changxin Memory Technologies, Inc.
发明人： WANG, Jia
IPC分类号： H03K19/017 , H03K19/0175 , H03K19/0185 , H03L7/07 , G06F13/40
摘要： A stagger signal generation circuit is provided. The stagger signal generation circuit includes: a stagger pulse generation circuit, configured to generate a first pulse signal according to a first control signal and generate a second pulse signal according to a second control signal, the first control signal and the second control signal being inverted signals, and the first pulse signal and the second pulse signal being stagger pulse signals; and a delay signal output circuit including G signal output circuits, G being an integer greater than or equal to 2. Each non-first-stage signal output circuits receives a delay output signal outputted by a respective previous-stage signal output circuit as an input signal of a current-stage signal output circuit, and a first-stage signal output circuit receives an initial input signal as an input signal of the first-stage signal output circuit. The embodiments of this application generate a first pulse signal and a second pulse signal with adjustable periods, and generate a delay signal with a controllable delay according to the first pulse signal and the second pulse signal, and an area of a circuit layout is small, and the power consumption of the circuit is low.

8. 发明授权

EP3731423B1 REDRIVER CHANNEL POWER UP IN CONVERGED INPUT/OUTPUT MODE 有权
公开(公告)号：EP3731423B1
公开(公告)日：2023-01-18
申请号：EP20169282.9
申请日：2020-04-14
发明人： DELSHADPOUR, Siamak , JUNG, Soon-Gil
IPC分类号： H04B3/36 , H04L25/20 , H03K19/0175 , H04L25/02

9. 发明授权

EP3435544B1 LEVEL CONVERSION CIRCUIT AND FINGERPRINT RECOGNITION DEVICE 有权
公开(公告)号：EP3435544B1
公开(公告)日：2022-09-14
申请号：EP17905433.3
申请日：2017-04-13
发明人： LI, Bo
IPC分类号： H03K19/0175 , H03K3/356

10. 发明授权

EP3422143B1 REGIONAL DESIGN-DEPENDENT VOLTAGE CONTROL AND CLOCKING 有权
公开(公告)号：EP3422143B1
公开(公告)日：2022-09-14
申请号：EP18174450.9
申请日：2018-05-25
发明人： LEWIS, David Michael , SCHMIT, Herman Henry
IPC分类号： G06F1/3296 , H03K5/159 , H03K19/00 , H03K19/0175 , H03K5/00

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