专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3401970A1 QUANTUM DOT LIGHT-EMITTING DIODE SUBSTRATE WITH BONDING LAYER AND PREPARATION METHOD THEREFOR 有权
公开(公告)号：EP3401970A1
公开(公告)日：2018-11-14
申请号：EP16840275.8
申请日：2016-08-02
申请人： BOE Technology Group Co., Ltd.
发明人： The designation of the inventor has not yet been filed
IPC分类号： H01L51/50 , H01L51/56
CPC分类号： H01L51/502 , B05D1/005 , H01L21/82 , H01L27/3211 , H01L27/3244 , H01L51/5004 , H01L51/5036 , H01L51/56
摘要： A quantum dot light-emitting diode substrate having a bonding layer and a method of preparing the same are provided. The quantum dot light-emitting diode substrate comprising a plurality of sub-pixel light-emitting regions (115), wherein each of the sub-pixel light-emitting regions comprises a light-emitting layer (114) comprising a bonding layer (106) and a quantum dot (103) bonded to the bonding layer. The quantum dot light-emitting diode substrate can be prepared with high resolution by a convenient process, and is suitable for mass production.

2. 发明授权

EP2804116B1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, PROGRAM, AND BOARD MANUFACTURING SYSTEM 有权
标题翻译：信息处理设备，信息处理方法，程序和板制造系统
公开(公告)号：EP2804116B1
公开(公告)日：2018-04-04
申请号：EP13775504.7
申请日：2013-02-05
申请人： Kabushiki Kaisha Zuken
发明人： WATANABE, Yasuyuki
IPC分类号： H05K3/00 , G06F17/50 , H05K3/12
CPC分类号： H05K3/0005 , G06F17/5072 , G06F17/5077 , G06F19/00 , G06F2217/12 , H01L21/82 , H01L39/24 , H05K3/1241 , H05K3/125
摘要： An information processing apparatus is configured to compute the shape of a conductive pattern to be formed on a board by a drawing apparatus that performs drawing on the board using conductive liquid droplets. The information processing apparatus includes an image data generation unit configured to generate image data in which dots each having a diameter determined according to a drawing condition of a conductive pattern by the drawing apparatus are arranged at respective positions which are indicated by data of a conductive pattern and at which conductive liquid droplets are to be landed.

3. 发明公开

EP2772948A3 Method for transferring semiconductor elements and for manufacturing flexible semiconductor devices 有权
标题翻译：一种用于传送半导体元件和半导体器件的制造方法flexibeln
公开(公告)号：EP2772948A3
公开(公告)日：2016-09-28
申请号：EP14156745.3
申请日：2014-02-26
申请人： Samsung Electronics Co., Ltd.
发明人： Cho, Eun-hyoung , Choi, Jun-hee , Sohn, Jin-seung , Moon, Chang-youl
IPC分类号： H01L33/00 , H01L33/44 , H01L31/0216 , H01S5/028 , H01L21/56 , H01L27/15 , H01L33/32
CPC分类号： H01L21/7806 , H01L21/02343 , H01L21/28 , H01L21/82 , H01L23/3192 , H01L27/153 , H01L31/035281 , H01L31/03926 , H01L31/1848 , H01L31/1856 , H01L31/1892 , H01L31/1896 , H01L33/0079 , H01L33/02 , H01L33/32 , H01L33/44 , H01L2933/0016 , H01S5/0217 , H01S5/32341 , Y02E10/544 , Y02P70/521
摘要： The present disclosure relates to a method of transferring semiconductor elements (200) from a non-flexible substrate (100) to a flexible substrate (450). The present disclosure also relates to a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements. The semiconductor elements (200) grown or formed on a non-flexible substrate (100) may be effectively transferred to a resin layer (450) while maintaining an arrangement of the semiconductor elements. The resin layer may function as a flexible substrate for supporting the vertical semiconductor elements (200).

4. 发明授权

EP2381478B1 Method of manufacturing an integrated circuit device 有权
标题翻译：一种用于制造集成电路器件的方法
公开(公告)号：EP2381478B1
公开(公告)日：2013-08-21
申请号：EP10011541.9
申请日：1999-02-03
申请人： Invensas Corporation
发明人： Badehi, Avner
IPC分类号： H01L27/146 , H01L21/70 , H01L23/31 , H01L25/10 , H01L31/0232 , H01L27/15 , H01L31/0203
CPC分类号： H01L31/02327 , H01L21/56 , H01L21/82 , H01L23/3114 , H01L24/02 , H01L24/97 , H01L25/105 , H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L27/15 , H01L31/02002 , H01L31/0203 , H01L31/02164 , H01L31/0232 , H01L31/125 , H01L31/186 , H01L33/0095 , H01L33/44 , H01L33/483 , H01L33/486 , H01L33/52 , H01L33/56 , H01L33/62 , H01L2221/68327 , H01L2224/0401 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01051 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A method of producing packaged optronic integrated circuit devices comprises (a) providing a transparent protective layer (26) overlying a first surface of a semiconductor wafer (20) including a plurality of dies; (b) forming notches extending into the wafer (20) from a second surface of the wafer (20), the notches being disposed at dice lanes between the dies; (c) providing an insulating layer (42) overlying the second surface of the wafer (20) and having an outer surface facing away from the wafer (20); (d) forming contacts electrically connected to the dies, the contacts extending outo the outer surface of the insulating layer (42); and then severing the transparent protective layer (26) to separate the dies from one another.

5. 发明授权

EP0585059B1 Vertical memory cell processing and structure manufactured by that processing 失效转让
标题翻译：一种用于制造由该方法生产的垂直型和结构的半导体存储器结构的方法
公开(公告)号：EP0585059B1
公开(公告)日：1999-05-12
申请号：EP93306575.7
申请日：1993-08-19
申请人： STMicroelectronics, Inc.
发明人： Zamanian, Mehdi , Worley, James Leon
IPC分类号： H01L21/82 , H01L27/11
CPC分类号： H01L21/82 , H01L27/11

6. 发明授权

EP0181191B1 Superconducting device 失效
标题翻译： Supraleiteranordnung
公开(公告)号：EP0181191B1
公开(公告)日：1996-02-28
申请号：EP85308009.1
申请日：1985-11-04
申请人： HITACHI, LTD.
发明人： Nishino, Toshikazu , Miyake, Mutsuko , Kawabe, Ushio , Harada, Yutaka , Aoki, Masaaki , Hirano, Mikio
IPC分类号： H01L39/22 , H01L39/24 , H01L27/18 , H01L21/82
CPC分类号： H01L39/228 , H01L21/82

7. 发明授权

EP0431522B1 Method for manufacturing semiconductor device 失效
标题翻译：一种用于制造半导体器件的工艺。
公开(公告)号：EP0431522B1
公开(公告)日：1995-02-15
申请号：EP90123107.6
申请日：1990-12-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinada, Kazuyoshi, c/o Intellectual Property Div. , Yoshida, Masayuki, c/o Intellectual Property Div. , Mizutani, Takahide, c/o Intellectual Property Div. , Hanada, Naoki, c/o Intellectual Property Division
IPC分类号： H01L21/82
CPC分类号： H01L27/11526 , H01L21/82 , H01L27/115 , H01L27/11539 , Y10S148/138

8. 发明公开

EP0386413A2 Complementary transistor structure and method for manufacture 失效
标题翻译： KomplementäreTransistorstruktur und deren Herstellungsverfahren。
公开(公告)号：EP0386413A2
公开(公告)日：1990-09-12
申请号：EP90100764.1
申请日：1990-01-15
申请人： International Business Machines Corporation
发明人： Harame, David L. , Patton, Gary L. , Stork, Johannes M.C.
IPC分类号： H01L27/082 , H01L21/82 , H01L27/08
CPC分类号： H01L21/82 , H01L27/0826
摘要： A transistor structure including a complementary pair of vertical bipolar transistors on a common semiconductor substrate. A first epitaxial layer (12) of semiconductor material of a first conductivity type is formed on the surface of a semiconductor substrate (10) of a second conductivity type, and a sub-emitter region for one of said complementary transistors being formed in said first layer (12). A sub-collector region (14) of a second conductivity type for the other of said complementary transistors is formed in the first layer (12). A second epitaxial layer (16) of semiconductor material of said second conductivity type is formed on the surface of said first layer (12). A third epitaxial layer (18) of semiconductor material of said first conductivity type is formed on the surface of said second layer (16). Deep recessed isolation regions (30, 32, 34) extend from the surface of said third layer (18) into said substrate (10), said deep isolation regions surround each of said transistors. Intrinsic base and collector regions (54, 56) of said one transistor are formed in said second and third layers (16, 18) respectively and intrinsic collector and base regions (58, 60) of said other transistor are formed in said second and third layers (16, 18) respectively. Shallow recessed isolation regions (44, 46, 48, 50, 52) are formed in said second and third layers (16, 18) surrounding said intrinsic base and collector regions (54, 58). A pair of extrinsic base regions (76, 78) of said first conductivity type for said other transistor and an extrinsic collector region (72) of said first conductivity type for said one transistor are formed on the surface of said third layer (18). An emitter reach-through region (74) of said first conductivity type is formed in said second and third layers (16, 18). An extrinsic base region (92) of said second conductivity type for said one transistor overlies said collector region (56) of said first conductivity type. A sub-collector reach-through region (94) of said second conductivity type is formed in said second and third layers (16, 18), and an emitter region (96) of said second conductivity type for said other transistor is formed overlying said base region (60) of said first conductivity type.
摘要翻译：一种在公共半导体衬底上包括一对互补的垂直双极晶体管的晶体管结构。第一导电类型的半导体材料的第一外延层（12）形成在第二导电类型的半导体衬底（10）的表面上，并且用于所述互补晶体管之一的子发射极区域形成在所述第一导电类型层（12）。在第一层（12）中形成用于另一个所述互补晶体管的第二导电类型的子集电极区（14）。所述第二导电类型的半导体材料的第二外延层（16）形成在所述第一层（12）的表面上。所述第一导电类型的半导体材料的第三外延层（18）形成在所述第二层（16）的表面上。深凹陷隔离区域（30,32,34）从所述第三层（18）的表面延伸到所述衬底（10）中，所述深隔离区域围绕每个所述晶体管。所述一个晶体管的本征基极和集电极区域（54,56）分别形成在所述第二和第三层（16,18）中，并且所述另一个晶体管的本征集电极和基极区域（58,60）形成在所述第二和第三层层（16,18）。在围绕所述本征基极和集电极区域（54,58）的所述第二和第三层（16,18）中形成浅凹陷的隔离区域（44,46,48,50,52）。在所述第三层（18）的表面上形成有用于所述另一晶体管的所述第一导电类型的一对非本征基区（76,78）和用于所述一晶体管的所述第一导电类型的非本征集电极区（72）。在所述第二和第三层（16,18）中形成有所述第一导电类型的发射极贯通区（74）。用于所述一个晶体管的所述第二导电类型的非本征基极区域覆盖所述第一导电类型的所述集电极区域（56）。在所述第二和第三层（16,18）中形成所述第二导电类型的子集电极贯通区（94），并且形成所述另一晶体管的所述第二导电类型的发射极区（96），覆盖所述第二导电类型所述第一导电类型的基极区域（60）。

9. 发明授权

EP0124358B1 Method for disconnecting interconnection using focused ion beam 失效
标题翻译：使用聚焦离子束断开互连的方法
公开(公告)号：EP0124358B1
公开(公告)日：1990-02-14
申请号：EP84302827.5
申请日：1984-04-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takigawa, Tadahiro c/o Patent Division
IPC分类号： H01L23/52 , H01L21/90
CPC分类号： H01L21/82 , H01L21/76892 , H01L23/525 , H01L23/5258 , H01L2924/0002 , H01L2924/00

10. 发明授权

EP0136952B1 A gate array 失效
标题翻译：盖茨阵列
公开(公告)号：EP0136952B1
公开(公告)日：1989-05-03
申请号：EP84401942.2
申请日：1984-09-28
申请人： FUJITSU LIMITED
发明人： Monma, Hideo , Ishiguro, Masato , Kawano, Tetsuo
IPC分类号： H01L27/02
CPC分类号： H01L27/11807 , H01L21/82

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式