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1. 发明公开

EP3336893A1 EMBEDDED SILICON SUBSTRATE FAN-OUT TYPE PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREFOR 审中-公开
公开(公告)号：EP3336893A1
公开(公告)日：2018-06-20
申请号：EP16834516.3
申请日：2016-06-15
申请人： Huatian Technology (Kunshan) Electronics Co., Ltd
发明人： YU, Daquan
IPC分类号： H01L23/488 , H01L23/06 , H01L21/56 , H01L23/373 , H01L21/50 , H01L23/18
CPC分类号： H01L24/19 , H01L21/56 , H01L23/06 , H01L23/18 , H01L23/488 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/83191 , H01L2224/92244 , H01L2224/97 , H01L2924/15153 , H01L2924/15155 , H01L2924/15156 , H01L2924/157 , H01L2924/3511 , H01L2924/37001 , H01L2224/83
摘要： Disclosed are an embedded silicon substrate fan-out type packaging structure and a manufacturing method therefor. A silicon substrate (1) is used to replace a molding compound to as a fan-out substrate, and fine wiring can be manufactured by making full use of the advantages of the silicon substrate (1). Structures of holes and grooves can be accurately etched by a mature silicon etching process. Chips (2) are embedded in the grooves on the silicon substrate (1), gaps between the chips (2) and the side walls of the grooves are filled with a polymer adhesive and partial solder balls (7) are fanned out on the surface of the silicon substrate (1), so that the packaging reliability can be improved. The process is simple and low in cost. Since the silicon substrate (1) has a good heat dissipation and a smaller warping degree, the improvement of the packaging heat dissipation is facilitated, adverse warping is overcome and smaller wiring line width is acquired, which is suitable for high-density packaging. With regard to the packaging structure, wafer plastic packaging can be eliminated, thus the process difficulty is reduced, the cost is significantly reduced and the yield is increased.

2. 发明公开

EP2654391A3 Flüssigkeitsgekühlte Anordnung mit anreihbaren Leistungshalbleitermodulen und mindestens einer Kondensatoreinrichtung und Leistungshalbleitermodul hierzu 审中-公开
标题翻译：可附接的功率半导体模块和至少一个电容器装置和功率半导体模块用于此目的的液体冷却装置
公开(公告)号：EP2654391A3
公开(公告)日：2017-02-15
申请号：EP13154128.6
申请日：2013-02-06
申请人： SEMIKRON Elektronik GmbH & Co. KG
发明人： Knebel, Markus , Kalla, Susanne , Maul, Andreas , Steger, Jürgen
IPC分类号： H05K7/20 , H01L25/07 , H01L25/11 , H01L23/473
CPC分类号： H01L23/473 , H01H9/52 , H01L23/06 , H01L23/34 , H01L23/36 , H01L23/40 , H01L23/4012 , H01L25/074 , H01L25/117 , H01L2924/0002 , H05K7/20 , H05K7/20927 , H01L2924/00
摘要： Es wird eine Anordnung mit einem Kühlkreislauf, einer Mehrzahl von anreihbaren Leistungshalbleitermodulen und mindestens einer Kondensatoreinrichtung vorgestellt, wobei ein Leistungshalbleitermodul eine leistungselektronische Schalteinrichtung und eine durchströmbare Kühleinrichtung zur Kühlung der Schalteinrichtung aufweist, die ein Kühlvolumen mindestens eine Kühlfläche und vier Anschlusseinrichtungen für eine Kühlflüssigkeit aufweist. Hierbei sind die Anschlusseinrichtungen paarweise an Hauptseiten des Leistungshalbleitermoduls angeordnet. Weiterhin sind die Leistungshalbleitermodule mit ihren Hauptseiten aneinandergereiht, indem korrespondierende Anschlusseinrichtungen aufeinanderfolgender Leistungshalbleitermodule mittelbar oder unmittelbar miteinander verbunden sind.
Hierzu ist zwischen mindestens zwei aufeinanderfolgenden Leistungshalbleitermodulen eine Kondensatoreinrichtung angeordnet, die ihrerseits mittels des Kühlkreislaufes der Anordnung direkt oder indirekt gekühlt wird.
摘要翻译：该装置具有一组在对用于与彼此连接的功率半导体模块的主侧面上布置的两个功率半导体模块（1）的主侧（2A，2B）的连接装置（110，120，130，140）的。一个电容器的功率半导体模块，其中，所述电容器直接或间接地通过一冷却回路冷却之间布置。一项所述的功率半导体模块的设置有功率电子开关（20），以及一个U形流动传导冷却装置（10）冷却电子开关的功率。因此独立claimsoft包括用于功率半导体模块。

3. 发明公开

EP1826817A1 Circuit module 审中-公开
标题翻译： Schaltkreismodul
公开(公告)号：EP1826817A1
公开(公告)日：2007-08-29
申请号：EP06251576.2
申请日：2006-03-23
申请人： FUJITSU LIMITED , Eudyna Devices Inc.
发明人： Shimura, Toshihiro c/o Fujitsu Limited , Ohashi, Yoji c/o Fujitsu Limited , Nunokawa, Mitsuji c/o Eudyna Devices Inc.
IPC分类号： H01L23/552 , H01L23/66
CPC分类号： H01L23/66 , H01L23/055 , H01L23/06 , H01L23/552 , H01L2224/0401 , H01L2224/04026 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/16152 , H01L2924/1616 , H01L2924/1617 , H01L2924/3011
摘要： In a high-frequency circuit module, a resistance film (7a) is formed on a side of a semiconductor circuit chip (6), mounted above a dielectric substrate (1) through a ground metal layer (4), facing the dielectric substrate. A distance from the ground metal layer (2) to the resistance film (7) is a 1/4 wavelength at a predetermined frequency, and the resistance film has a sheet resistance equal to a characteristic impedance of air. A second dielectric substrate (12) with a metal layer (13) formed on a side opposite to the resistance film (7a) can be mounted. When being adhered to the second dielectric substrate (12), the resistance film (7a) has a characteristic impedance determined by a permittivity of a material of the semiconductor circuit chip (6). When it is formed spaced apart from the semiconductor circuit chip, the resistance film has a sheet resistance equal to a characteristic impedance of air. The thickness of the second dielectric substrate is a 1/4 wavelength in a desired frequency.
摘要翻译：在高频电路模块中，电阻膜（7a）形成在半导体电路芯片（6）的一侧，通过接地金属层（4）安装在电介质基片（1）的上方，面对电介质基片。距接地金属层（2）至电阻膜（7）的距离为预定频率的1/4波长，电阻膜具有与空气的特性阻抗相等的薄层电阻。可以安装具有形成在与电阻膜（7a）相对的一侧上的金属层（13）的第二电介质基板（12）。当粘附到第二电介质基板（12）时，电阻膜（7a）具有由半导体电路芯片（6）的材料的介电常数确定的特性阻抗。当其形成为与半导体电路芯片间隔开时，电阻膜具有等于空气的特性阻抗的薄层电阻。第二电介质基板的厚度为期望频率的1/4波长。

4. 发明授权

EP0839078B1 Method of manufacturing Si-Al alloys for electronic packaging 失效
标题翻译：一种用于制备的Al-Si合金用于电子部件的美国包装过程
公开(公告)号：EP0839078B1
公开(公告)日：2001-09-19
申请号：EP96924997.8
申请日：1996-07-18
申请人： OSPREY METALS LIMITED
发明人： LEATHAM, Alan, George , OGILVY, Andrew, Josef, Widawski , ELIAS, Luis
IPC分类号： B22D23/00 , B22F9/08 , C22C28/00 , H01L23/36 , H01L23/373
CPC分类号： C22C1/1042 , B22F3/115 , C22C1/04 , C22C25/00 , C22C32/0063 , H01L23/06 , H01L23/142 , H01L2924/0002 , H01L2924/01079 , Y10T428/12486 , H01L2924/00
摘要： A method of producing a silicon based alloy is described which comprises melting a silicon alloy containing greater than 50 wt.% silicon and preferably including aluminium. The melted alloy is then inert gas atomized to produce powder or a spray formed deposit in which the silicon forms a substantially continuous phase made up of fine, randomly oriented crystals in the microstructure. The alloy produced by the method has particularly useful application in electronics packaging materials and a typical example comprises an alloy of 70 wt.% silicon and 30 wt.% aluminium. Such an alloy is an engineering material which, for example, is machinable.

5. 发明公开

EP0719453A4 FLIP CHIP IN METAL ELECTRONIC PACKAGES 失效
标题翻译：金属制品中的切片，ELEKTRONISCHEN PACKUNGEN
公开(公告)号：EP0719453A4
公开(公告)日：1998-08-19
申请号：EP94926028
申请日：1994-08-29
申请人： OLIN CORP
发明人： BRADEN JEFFREY S , MAHULIKAR DEEPAK
IPC分类号： H01L21/60 , H01L23/04 , H01L23/055 , H01L23/057 , H01L23/06 , H01L23/12 , H01L23/50 , H01L23/22 , H01L23/48 , H05K7/20
CPC分类号： H01L23/06 , H01L23/04 , H01L23/055 , H01L23/057 , H01L2224/16 , H01L2224/73253 , H01L2924/01025 , H01L2924/01046 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152
摘要： There is provided an electronic package (10) for encapsulating a flip chip bonded integrated circuit device (12). A metallic base component (14) and a cover component (16) define a cavity (18). A substrate (28) is disposed within the cavity (18). The substrate (28) contains a first metallization array (30) and a second metallization array (32). The input/output pads (50) of the integrated circuit device (12) are bonded to the first metallization array (30) and the inner leads (22) of a leadframe (20) are bonded to the second metallization array (32). When the metallic base component (14) and cover component (16) are bonded (26) together with a leadframe (20) disposed therebetween, the substrate (28), inner leads (22) and integrated circuit device (12) are encapsulated within the cavity (18).
摘要翻译：提供了一种用于封装倒装芯片接合集成电路器件（12）的电子封装（10）。金属基部件（14）和盖部件（16）限定空腔（18）。衬底（28）设置在空腔（18）内。衬底（28）包含第一金属化阵列（30）和第二金属化阵列（32）。集成电路器件（12）的输入/输出焊盘（50）接合到第一金属化阵列（30），并且引线框架（20）的内部引线（22）被结合到第二金属化阵列（32）。当金属基座部件（14）和盖部件（16）与布置在其间的引线框架（20）结合在一起时，衬底（28），内部引线（22）和集成电路器件（12）被封装在空腔（18）。

6. 发明公开

EP0700083A2 Aluminium alloy base semiconductor packages 失效
标题翻译： Halbleiterpackungen auf Basis von Aluminiumlegierung
公开(公告)号：EP0700083A2
公开(公告)日：1996-03-06
申请号：EP95117178.4
申请日：1989-09-14
申请人： OLIN CORPORATION
发明人： The designation of the inventor has not yet been filed
IPC分类号： H01L23/057 , H01L23/10 , H01L23/14 , H01L23/06
CPC分类号： H01L23/06 , H01L23/057 , H01L23/10 , H01L23/142 , H01L24/48 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01012 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , Y10T29/49121 , H01L2224/45099 , H01L2924/00
摘要： The present invention relates to a package (10) adapted to house an electronic device (12), such as a semiconductor integrated circuit. The package (10) components are comprised of aluminum or an aluminum based alloy. At least a portion of the surfaces of the package components are anodized to enhance corrosion resistance and increase bond strength. The aluminum based packages are characterized by lighter weight than copper based packages and better thermal conductivity than plastic based packages.
摘要翻译：本发明涉及一种适于容纳诸如半导体集成电路的电子设备（12）的封装（10）。封装（10）部件由铝或铝基合金构成。包装部件的表面的至少一部分被阳极氧化以增强耐腐蚀性并增加粘结强度。基于铝的包装的特征在于比基于铜的包装更轻的重量和比基于塑料的包装更好的导热性。

7. 发明公开

EP0431261A1 Integrated circuit package with cap and device of the same material 失效
标题翻译：包具有盖和相同的材料的装置的集成电路。
公开(公告)号：EP0431261A1
公开(公告)日：1991-06-12
申请号：EP90115893.1
申请日：1990-08-20
申请人： International Business Machines Corporation
发明人： Bregman, Mark Fielding , Horton, Robert Raymond , Noyan, Ismail Cevdet , Palmer, Michael Jon
IPC分类号： H01L23/04 , H01L23/06 , H01L23/14 , H01L21/52
CPC分类号： H01L21/4803 , H01L23/04 , H01L23/06 , H01L23/147 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： A thermally matched integrated circuit package comprising a semiconductor substrate; at least one semiconductor electronic device mounted on said substrate; means for providing electrical connections to said at least one semiconductor electronic device and to said substrate; and a semiconductor cap, disposed over said at least one device, wherein the cap is directly attached to said substrate and further wherein said substrate, said at least one device, and said cap are all formed from the same semiconductor material to assure no thermal mismatch therebetween. The cap comprises at least one cavity which is disposed over at least one semiconductor electronic device. The cap may be fabricated utilizing anisotropic etching techniques or via electro-discharge machining. Hermetically sealed and nonhermetically sealed caps are both contemplated, as well as a grooved cap having an increased surface area to enhance its inherent cooling capacity. The invention is well suited to enhancing the performance of large scale multichip carrier modules.
摘要翻译：热匹配的集成电路封装，包括：半导体衬底; 在安装在所述基板的至少一个半导体电子器件; 装置，用于提供到所述的电连接的至少一个半导体电子器件和所述的底物; 和半导体帽，设置在所述至少一个设备，worin盖被直接附连到所述基板，此外worin所述基板，所述至少一个设备，并且所述帽都是从相同的半导体材料形成，以确保没有热失配有间。帽包括至少一个腔，其全部被设置在至少一个半导体电子器件。该盖可以制造利用各向异性蚀刻技术或通过放电加工。密封和密封nonhermetically帽都是预期的，以及在增加的表面积具有以提高其内在的冷却能力的开槽帽。本发明非常适合于提高的大规模多芯片载体模块的性能。

8. 发明公开

EP3218930A4 PACKAGE FOR ELECTRONIC SYSTEM HAVING SEMICONDUCTOR CHIPS 有权转让
公开(公告)号：EP3218930A4
公开(公告)日：2018-07-25
申请号：EP15859853
申请日：2015-11-11
申请人： TEXAS INSTRUMENTS INC
发明人： LOPEZ OSVALDO JORGE , NOQUIL JONATHAN ALMERIA , GREBS THOMAS EUGENE , MOLLOY SIMON JOHN
IPC分类号： H01L25/065 , H01L23/02 , H01L23/14 , H01L25/03 , H01L25/07 , H01L29/06
CPC分类号： H01L25/0657 , H01L21/50 , H01L23/053 , H01L23/06 , H01L23/13 , H01L23/147 , H01L23/49844 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/071 , H01L25/074 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/06181 , H01L2224/2919 , H01L2224/32145 , H01L2224/83851 , H01L2224/94 , H01L2224/97 , H01L2225/00 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06589 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01079 , H01L2924/04642 , H01L2924/04941 , H01L2924/05042 , H01L2924/05442 , H01L2924/10155 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10329 , H01L2924/1033 , H01L2924/1037 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/1427 , H01L2924/15156 , H01L2924/157 , H01L2224/83
摘要： An electronic system comprises a first chip (101) of single-crystalline semiconductor including a first electronic device embedded in a second chip (102) of single-crystalline semiconductor shaped as a container having a slab (104) bordered by ridges (103), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slab 130 bordered by retaining walls 131 and including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip; and the first and second electronic devices are connected to the container by embedding the second chip in the container, wherein the nested first and second chips operate as an electronic system and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.

9. 发明公开

EP3240125A4 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP3240125A4
公开(公告)日：2018-01-03
申请号：EP15872119
申请日：2015-08-05
申请人： PANASONIC IP MAN CO LTD
发明人： UEDA NAOTO , OOMORI KOUJI , YOSHIDA TAKAYUKI , MOTOFUJI TAKUMA
IPC分类号： H01S5/024 , H01L21/60 , H01L23/373 , H01L23/40 , H01L23/48 , H01L25/07 , H01L25/18 , H01L29/861 , H01S5/022 , H01S5/042
CPC分类号： H01L23/3731 , H01L23/06 , H01L23/13 , H01L23/142 , H01L23/36 , H01L23/3736 , H01L23/4006 , H01L23/48 , H01L24/13 , H01L24/16 , H01L25/07 , H01L25/18 , H01L29/861 , H01L2023/4043 , H01L2023/4068 , H01L2224/13144 , H01L2224/16245 , H01L2924/0002 , H01L2924/1203 , H01L2924/12042 , H01L2924/15153 , H01L2924/16235 , H01L2924/16251 , H01S5/02236 , H01S5/024 , H01S5/042 , H01S5/0425 , H01L2924/00
摘要： A semiconductor device according to the present disclosure includes an electrically conductive first electrode block, an electrically conductive submount, an insulating layer, a semiconductor element, an electrically conductive bump, and an electrically conductive second electrode block. The submount is provided in a first region of the upper surface of the first electrode block, and electrically connected to the first electrode block. The semiconductor element is provided on the submount, and has a first electrode electrically connected to the submount. The bump is provided on the upper surface of a second electrode, opposite the first electrode, of the semiconductor element, and electrically connected to the second electrode. A third region of the lower surface of the second electrode block is electrically connected to the bump via an electrically conductive metal layer. An electrically conductive metal sheet is provided between the metal layer and the bump.

10. 发明公开

EP3044162A1 METHOD OF WAFER-LEVEL HERMETIC PACKAGING WITH VERTICAL FEEDTHROUGHS 有权
标题翻译： VERFAHREN ZUR HERMETISCHEN VERPACKUNG AUF WAFEREBENE MIT VERTIKALENDURCHFÜHRUNGEN
公开(公告)号：EP3044162A1
公开(公告)日：2016-07-20
申请号：EP13784037.7
申请日：2013-09-11
申请人： Alper, Said Emre , Torunbalci, Mustafa Mert , Akin, Tayfun
发明人： Alper, Said Emre , Torunbalci, Mustafa Mert , Akin, Tayfun
IPC分类号： B81C1/00
CPC分类号： B81C1/00301 , B81B2207/095 , B81C2203/0118 , B81C2203/0145 , B81C2203/031 , B81C2203/035 , B81C2203/036 , B81C2203/0792 , H01L23/02 , H01L23/04 , H01L23/06 , H01L23/10 , H01L2224/48463
摘要： A wafer-level packaging method for MEMS structures that are desired to be encapsulated in a hermetic cavity and that need the transfer of at least a single or multiple electrical leads to the outside of the cavity without destroying the hermeticity of the cavity. Lead transfer is achieved using vertical feedthroughs that are patterned on the capping substrate within the same fabrication step to produce the encapsulating cavity. Furthermore, the structure of the vertical feedthroughs and via openings to reach these feedthroughs are arranged in such a way that conventional wirebonding would be sufficient to connect the vertical feedthroughs to the outer world, without a need for conductor-refill inside the via openings. The method is compatible with low-temperature thermocompression-based bonding/sealing processes using various sealing materials such as thin- film metals and alloys, and also with the silicon-glass anodic or silicon-silicon fusion bonding processes.
摘要翻译：用于MEMS结构的晶片级封装方法，其希望被封装在密封腔中，并且需要将至少一个或多个电引线传送到空腔的外部，而不破坏腔的气密性。使用在相同制造步骤中的封盖基板上图案化的垂直馈通来实现引线转移以产生封装腔。此外，到达这些馈通的垂直馈通和通孔的结构被布置成使得常规的引线键合足以将垂直馈通连接到外部世界，而不需要在通孔开口内部进行导体重新填充。该方法与使用各种密封材料如薄膜金属和合金以及硅玻璃阳极或硅 - 硅熔合工艺的低温热压基接合/密封工艺兼容。

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