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1. 发明公开

EP3379537A2 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP3379537A2
公开(公告)日：2018-09-26
申请号：EP17195769.9
申请日：2017-10-10
申请人： Renesas Electronics Corporation
发明人： TAKEUCHI, Kan , TSUCHIYA, Fumio , KONISHI, Shinya
IPC分类号： G11C7/04 , G11C16/34
CPC分类号： G01R31/2642 , G01R31/2628 , G01R31/2817 , G01R31/2856 , G01R31/2874 , G01R31/30 , G06F12/16 , G11C7/04 , G11C16/349 , G11C29/12015 , G11C2029/5002 , H03K3/0315
摘要： To provide a semiconductor device that can predict wear-out failure with high accuracy based on an accumulated value of degradation stress, such as a power-source voltage or an environmental temperature, imposed to the semiconductor device, the semiconductor device includes a first circuit that holds a first accumulated degradation stress count value, a second circuit that holds a second accumulated degradation stress count value, a third circuit that holds a count value of an accumulated operating time or a value corresponding thereto, and a fourth circuit or an operating unit that receives the first accumulated degradation stress count value, the second accumulated degradation stress count value, and the count value of the accumulated operating time or the value corresponding to the value of the accumulated operating time.

2. 发明公开

EP1990805A1 RAM MACRO AND TIMING GENERATING CIRCUIT FOR SAME 有权
标题翻译： RAM-MAKRO展出时代ERZEUGUNGSSCHALTUNGDAFÜR
公开(公告)号：EP1990805A1
公开(公告)日：2008-11-12
申请号：EP06714793.4
申请日：2006-02-28
申请人： Fujitsu Ltd.
发明人： IJITSU, Kenji
IPC分类号： G11C29/50 , G11C11/413
CPC分类号： G11C29/14 , G11C11/41 , G11C29/12015
摘要： A timing generating circuit 13 generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a testing circuit 14. The control clock (1) is a signal the phase of which is delayed by a predetermined amount with reference to the clock CLK. This predetermined amount can be set/changed with an external test signal. The test clock (2) is nearly an inversion signal of the clock CLK. The testing circuit 14 generates various types of control signals (4) based on either of the clocks (1) and (2), and distributes the signals to a controlling circuit 12. Which of the clocks (1) and (2) is selected in the testing circuit 14 can be set with an external test signal.
摘要翻译：定时发生电路13基于外部输入的时钟CLK产生控制时钟（1）和测试时钟（2），并将产生的时钟输出到测试电路14.控制时钟（1）是信号的相位其被参考时钟CLK延迟预定量。该预定量可以通过外部测试信号来设定/改变。测试时钟（2）几乎是时钟CLK的反相信号。测试电路14基于时钟（1）和（2）中的任一个产生各种类型的控制信号（4），并将信号分配给控制电路12.选择哪个时钟（1）和（2）在测试电路14中可以设置外部测试信号。

3. 发明公开

EP1806751A1 Programmable delay introducing circuit in self timed memory 审中-公开
标题翻译：在einem selbstzeitgesteuerten Speicher的ProgrammierbareVerzögerungseinführungsschaltung
公开(公告)号：EP1806751A1
公开(公告)日：2007-07-11
申请号：EP06127150.8
申请日：2006-12-22
申请人： STMicroelectronics Pvt. Ltd.
发明人： Kohli, Nishu , Bhargava, Mudit , Kumar, Shishir
IPC分类号： G11C7/22 , G11C7/06 , G11C7/08
CPC分类号： G11C7/227 , G11C7/06 , G11C7/08 , G11C7/22 , G11C7/222 , G11C29/12015 , G11C29/14 , G11C29/50 , G11C29/50012
摘要： A novel method for introducing delays in self timed memories is disclosed. In the proposed method, delays are introduced by introducing a capacitance on the path of signal to be delayed. The capacitances are realized by using idle lying metal layers in the circuit. The signal to be delayed is connected to these idle lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since, in the proposed method, idle-lying metal capacitances are utilized, the circuit can be implemented using minimum amount of additional hardware. Also delay provided by the proposed circuitry is a function of memory cell spice characteristics and core parasitic capacitances.
摘要翻译：公开了一种用于引入自定时存储器中的延迟的新方法。在所提出的方法中，通过在要延迟的信号的路径上引入电容来引入延迟。电容通过在电路中使用空闲的躺着金属层来实现。要延迟的信号通过可编程开关连接到这些空闲的电平。引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。开关的状态由延迟引入电路外部提供的延迟代码来控制。由于在所提出的方法中，利用空闲的金属电容，所以可以使用最小量的附加硬件来实现该电路。由所提出的电路提供的延迟也是存储单元香料特性和核心寄生电容的函数。

4. 发明公开

EP3394856A1 FLEXIBLE DLL (DELAY LOCKED LOOP) CALIBRATION 有权
公开(公告)号：EP3394856A1
公开(公告)日：2018-10-31
申请号：EP16879804.9
申请日：2016-11-23
申请人： Intel Corporation
发明人： QAWAMI, Shekoufeh , ALLEN, Michael , SUNDARAM, Rajesh
IPC分类号： G11C7/22 , H03L7/081
CPC分类号： G11C7/222 , G06F13/1689 , G11C29/022 , G11C29/023 , G11C29/1201 , G11C29/12015 , G11C2207/2254 , Y02D10/14
摘要： A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

5. 发明授权

EP1390951B1 DYNAMISCHER SPEICHER UND VERFAHREN ZUM TESTEN EINES DYNAMISCHEN SPEICHERS 有权
标题翻译：动态内存以及检验方法动态存储器
公开(公告)号：EP1390951B1
公开(公告)日：2005-03-16
申请号：EP02740591.9
申请日：2002-05-13
申请人： Infineon Technologies AG
发明人： OHLHOFF, Carsten
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/14
摘要： The invention relates to a dynamic memory comprising a memory cell array (10), a test controller (12) for testing the memory cell array (10) and an oscillator (14) for controlling the refreshing of said memory cell array (10). According to the invention, said memory includes means (16) for using the oscillator (14) as a time base for the test controller. Hereby, a slow time base is achieved, which may be used for different self-tests of the memory.

6. 发明公开

EP1390951A2 DYNAMISCHER SPEICHER UND VERFAHREN ZUM TESTEN EINES DYNAMISCHEN SPEICHERS 有权
标题翻译：动态内存以及检验方法动态存储器
公开(公告)号：EP1390951A2
公开(公告)日：2004-02-25
申请号：EP02740591.9
申请日：2002-05-13
申请人： Infineon Technologies AG
发明人： OHLHOFF, Carsten
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C11/401 , G11C29/14
摘要： The invention relates to a dynamic memory comprising a memory cell array (10), a test controller (12) for testing the memory cell array (10) and an oscillator (14) for controlling the refreshing of said memory cell array (10). According to the invention, said memory includes means (16) for using the oscillator (14) as a time base for the test controller. Hereby, a slow time base is achieved, which may be used for different self-tests of the memory.

7. 发明公开

EP0805460A1 Integrated circuit having a built-in selft-test arrangement 失效
标题翻译： Integrierte Schaltung mit einer eingebauten Selbsttestanordnung
公开(公告)号：EP0805460A1
公开(公告)日：1997-11-05
申请号：EP97302975.4
申请日：1997-04-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hii, Kuong Hua , Powell, Theo J. , Cline, Danny R.
IPC分类号： G11C29/00 , G06F11/27 , G01R31/3187
CPC分类号： G01R31/30 , G06F1/08 , G06F11/27 , G06F2201/88 , G11C11/401 , G11C29/12015 , G11C29/14 , G11C29/16 , G11C29/36 , G11C29/38 , G11C29/50 , G11C29/56012
摘要： An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit
摘要翻译：集成电路具有内置的自检（BIST）布置（60）。内置的自检装置包括存储测试算法指令的只读存储器（ROM）（140）。 ROM逻辑电路（410）接收从只读存储器读取的指令，并根据指令产生一组输出信号。 BIST寄存器420接收并存储来自用于控制集成电路的自检的逻辑电路的输出信号组

8. 发明公开

EP3379537A3 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP3379537A3
公开(公告)日：2018-10-03
申请号：EP17195769.9
申请日：2017-10-10
申请人： Renesas Electronics Corporation
发明人： TAKEUCHI, Kan , TSUCHIYA, Fumio , KONISHI, Shinya
IPC分类号： G11C7/04 , G11C16/34
CPC分类号： G01R31/2642 , G01R31/2628 , G01R31/2817 , G01R31/2856 , G01R31/2874 , G01R31/30 , G06F12/16 , G11C7/04 , G11C16/349 , G11C29/12015 , G11C2029/5002 , H03K3/0315
摘要： To provide a semiconductor device that can predict wear-out failure with high accuracy based on an accumulated value of degradation stress, such as a power-source voltage or an environmental temperature, imposed to the semiconductor device, the semiconductor device includes a first circuit that holds a first accumulated degradation stress count value, a second circuit that holds a second accumulated degradation stress count value, a third circuit that holds a count value of an accumulated operating time or a value corresponding thereto, and a fourth circuit or an operating unit that receives the first accumulated degradation stress count value, the second accumulated degradation stress count value, and the count value of the accumulated operating time or the value corresponding to the value of the accumulated operating time.

9. 发明公开

EP2149885A1 Integrated circuit and method for testing the circuit 有权
标题翻译： Integrierte Schaltung und Verfahren zum Testen der Schaltung
公开(公告)号：EP2149885A1
公开(公告)日：2010-02-03
申请号：EP09162648.1
申请日：2009-06-13
申请人： Fujitsu Microelectronics Limited
发明人： Hiraide, Takahisa
IPC分类号： G11C29/14
CPC分类号： G11C29/14 , G11C29/1201 , G11C29/12015 , G11C2029/0401
摘要： An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated.
摘要翻译：集成电路包括存储器; 用于测试存储器的存储器测试电路; 以及输入/输出端口，其中存储器测试电路包括输出存储器的输出的锁存电路，根据第一时钟信号改变要访问的存储器的地址，并且对应于改变的存储器的存储器的输出地址按照具有第一时钟信号的整数倍的周期的锁存信号锁存，锁存电路的数据以锁存信号的周期经由输入/输出端口输出，存储单元的地址对应到由锁存电路锁存的存储器的输出改变，并且锁存器和输出被重复。

10. 发明公开

EP1732082A3 A memory architecture with BIST 审中-公开
标题翻译：内存架构BIST
公开(公告)号：EP1732082A3
公开(公告)日：2007-11-21
申请号：EP06011188.7
申请日：2006-05-31
申请人： STMicroelectronics Pvl. Ltd.
发明人： Dubey, Prashant
IPC分类号： G11C29/04
CPC分类号： G11C29/12015 , G11C29/003 , G11C29/1201 , G11C29/20 , G11C29/40 , G11C2029/0405 , G11C2029/3602
摘要： This invention relates to a memory architecture with built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. A method for in-built testing of a memory architecture is also described.

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