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1. 发明公开

EP3254287A1 APPARATUSES AND METHODS FOR MEMORY DEVICE AS A STORE FOR PROGRAM INSTRUCTIONS 审中-公开
标题翻译：记忆装置作为程序指令的存储装置和方法
公开(公告)号：EP3254287A1
公开(公告)日：2017-12-13
申请号：EP16746991.5
申请日：2016-01-27
申请人： Micron Technology, Inc.
发明人： ZAWODNY, Jason T. , WHEELER, Kyle B. , MURPHY, Richard C.
IPC分类号： G11C7/06 , G11C11/413 , G11C11/416
CPC分类号： G06F12/0238 , G06F12/0888 , G06F15/7821 , G06F2212/202 , G06F2212/603 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1036 , G11C8/12 , G11C11/4087 , G11C11/4096
摘要： The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

2. 发明授权

EP3114689B1 VARIABLE READ DELAY SYSTEM 有权
标题翻译：可变读取延迟系统
公开(公告)号：EP3114689B1
公开(公告)日：2017-09-20
申请号：EP15718001.9
申请日：2015-03-20
申请人： Qualcomm Incorporated
发明人： KIM, Jung Pill , KIM, Taehyun , KIM, Sungryul , DONG, Xiangyu
IPC分类号： G11C11/16 , G11C16/26 , G11C16/30 , G11C29/02 , G11C29/30 , G11C29/52 , G11C29/04 , G11C7/08 , G11C7/06 , G11C7/10 , G11C13/00 , G11C14/00 , G06F11/10
CPC分类号： G11C29/026 , G06F11/106 , G06F11/1072 , G06F11/1076 , G11C7/06 , G11C7/08 , G11C7/1006 , G11C7/1072 , G11C11/16 , G11C11/1673 , G11C13/004 , G11C14/0081 , G11C14/009 , G11C16/26 , G11C16/30 , G11C29/30 , G11C29/52 , G11C2029/0411

3. 发明公开

EP3002788A3 DISPOSITIF A CELLULES MEMOIRES SRAM COMPORTANT DES MOYENS DE POLARISATION DES CAISSONS DES TRANSISTORS DES CELLULES MEMOIRES 有权
标题翻译： VORRICHTUNG MIT SRAM-SPEICHERZELLEN，DIE POLARISIERUNGSMITTEL DERTRANSISTORGEHÄUSEDER SPEICHERZELLEN UMFASST
公开(公告)号：EP3002788A3
公开(公告)日：2016-06-22
申请号：EP15184711.8
申请日：2015-09-10
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： THOMAS, Olivier , GIRAUD, Bastien , MAKOSIEJ, Adam
IPC分类号： H01L27/11 , H01L27/12 , H01L21/84 , H01L29/786
CPC分类号： G11C11/419 , G11C7/06 , G11C29/44 , H01L21/84 , H01L27/1104 , H01L27/1116 , H01L27/1203 , H01L29/786
摘要： Dispositif mémoire (100) comportant :
- une matrice de plusieurs colonnes de cellules mémoires SRAM comportant chacune des transistors formant un point mémoire, un port de lecture et un port d'écriture, et tels que les transistors du port de lecture et/ou les transistors de type P comportent un deuxième caisson (133) d'un type de conductivité opposé à celui d'un premier caisson (125) des autres transistors ;
- des moyens (136, 138, 140, 142) de polarisation des deuxièmes caissons, aptes à sélectionner et appliquer des valeurs de polarisation sur les deuxièmes caissons, comprenant :
• un circuit mémoire des états de polarisation des deuxièmes caissons pour chaque colonne ou groupe de colonnes ;
• un circuit de sélection appliquant sur les deuxièmes caissons un potentiel de polarisation selon l'une des valeurs reçues en entrée, en fonction de l'état de polarisation mémorisé associé à la colonne ou au groupe de colonnes.
摘要翻译：存储器件包括几列SRAM存储器单元的矩阵，每个SRAM存储单元包括形成存储点的晶体管，读端口和写端口，并且使得读端口和/或P型晶体管的晶体管包括第二阱其导电类型与其它晶体管的第一阱相反。存储器件还包括用于第二阱的偏振单元，其能够选择并施加第二阱上的极化电位，包括用于每列或一组列的第二阱的极化状态的存储电路，以及应用根据作为输入接收的值之一，第二阱上的极化电位作为与列或一组列相关联的存储的偏振状态的函数。

4. 发明公开

EP3025346A1 APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY 有权
标题翻译：器件和方法对于运行比较使用集合电路实现
公开(公告)号：EP3025346A1
公开(公告)日：2016-06-01
申请号：EP14829677.5
申请日：2014-07-10
申请人： Micron Technology, Inc.
发明人： MANNING, Troy A.
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C7/10 , G11C7/1006 , G11C7/1048 , G11C7/12 , G11C11/4091 , G11C11/4096 , G11C15/043
摘要： The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
摘要翻译：本公开内容包括与执行比较和/或报告操作中使用感测电路的方法和装置。的示例性方法可以包括存储器阵列的电压的输入/输出（IO）线的充电。该方法可包括确定是否采存储在存储器阵列中的数据相匹配的比较值。是否存储数据的比较值相匹配的确定可以包括激活一个数的存储器阵列的存取线。所述确定可以包括：感测一个数耦合到的接入线路的数目的存储器单元。所述确定可以包括感测是否IO线的电压响应于选定的解码器线对应于存储器单元的数量的激活而改变。

5. 发明公开

EP2984651A2 MEMORY WITH LOCAL-/GLOBAL BIT LINE ARCHITECTURE AND ADDITIONAL CAPACITANCE FOR GLOBAL BIT LINE DISCHARGE IN READING 有权
标题翻译：带有全局位线放电READING局部/全局位线和附加容量内存
公开(公告)号：EP2984651A2
公开(公告)日：2016-02-17
申请号：EP14716379.4
申请日：2014-04-01
申请人： Surecore Limited
发明人： STANSFIELD, Anthony
IPC分类号： G11C11/419 , G11C7/12 , G11C7/18
CPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： There is provided a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells that are grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, when a memory cell of the memory cell group is being read, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group.
摘要翻译：提供了一种存储器单元，其包括一个或连接到一个读出放大器更全局位线，和存储单元的多元性没有被分组为存储器单元组的复数，每个存储器单元组具有一个或多个局部位线可操作地连接到每个存储器单元组中的存储器单元。每个存储单元组被配置寻求的是，当正被读取的存储单元组的存储单元，该存储单元组的一个或多个本地的位线作为输入被提供到逻辑电路，而不是连接到全局位线，被配置成所述逻辑电路，以使电容元件被连接到在后的存储单元组的一个或多个本地的位线的状态的依赖性的所述一个或多个全局位线之一。

6. 发明公开

EP2805329A1 SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER 审中-公开
标题翻译：系统和方法用于修改检测放大器的激活
公开(公告)号：EP2805329A1
公开(公告)日：2014-11-26
申请号：EP13709536.0
申请日：2013-01-14
申请人： Marvell World Trade Ltd.
发明人： SON, Moon-hae , LEE, Peter , LEE, Winston
IPC分类号： G11C11/419 , G11C7/22 , G11C7/08
CPC分类号： G11C7/06 , G11C7/08 , G11C7/227 , G11C11/419
摘要： Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel.

7. 发明授权

EP2289070B1 HIGH SPEED SENSE AMPLIFIER ARRAY AND METHOD FOR NONVOLATILE MEMORY 有权转让
标题翻译：快速读出放大器串和方法非易失性存储器
公开(公告)号：EP2289070B1
公开(公告)日：2014-05-07
申请号：EP09755420.8
申请日：2009-04-01
申请人： SanDisk Technologies Inc.
发明人： NGUYEN, Hao, Thai , MUI, Man Lung , LEE, Seungpil , ZHANG, Fanglin , WANG, Chi-Ming
IPC分类号： G11C7/02 , G11C11/56 , G11C16/26 , G11C7/06 , G11C16/04
CPC分类号： G11C16/26 , G11C7/02 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C2211/5634

8. 发明公开

EP2553684A4 SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES 有权
标题翻译：系统和方法的非易失性存储器用于确定选择性/差分阈值电压功能
公开(公告)号：EP2553684A4
公开(公告)日：2013-11-20
申请号：EP11763403
申请日：2011-03-30
申请人： SILICON STORAGE TECH INC
发明人： TRAN HIEU VAN , SAHA SAMAR
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C16/28 , H01L21/28282 , H01L21/823412 , H01L21/823807 , H01L29/1083 , H01L29/42368 , H01L29/4238 , H01L29/66833 , H01L29/7835 , H01L29/792
摘要： Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.
摘要翻译：系统和方法是游离缺失盘用于通过使用具有差的阈值电压的MOS晶体管的提供选择性阈值电压特性。在一个示例性实施例，提供了一种金属氧化物半导体器件，包括具有源极区，漏极区和它们之间的沟道区，在沟道区的绝缘层上，且绝缘层的栅极部分的半导体材料的基片。更以上，对于该装置中，绝缘层和/或结型区域的形状或植入的形状是变化的尺寸的作为栅 - 漏和栅 - 源极结之间提供差的阈值电压之间它们。

9. 发明授权

EP2132747B1 SPATIALLY DISTRIBUTED AMPLIFIER CIRCUIT 失效转让
标题翻译：空间分布式放大器电路
公开(公告)号：EP2132747B1
公开(公告)日：2013-04-24
申请号：EP08744808.0
申请日：2008-03-31
申请人： Sandisk 3D LLC
发明人： FASOLI, Luca G. , AL-SHAMMA, Ali , SO, Kenneth K.
IPC分类号： G11C7/08 , G11C7/06 , G11C7/10 , G11C11/408 , G11C8/08
CPC分类号： G11C7/06 , G11C7/08 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C11/4085

10. 发明公开

EP2562760A2 Memory device readout using multiple sense times 有权
标题翻译： Speichervorrichtungsauslesung mit mehrerenFühlzeitpunkten
公开(公告)号：EP2562760A2
公开(公告)日：2013-02-27
申请号：EP12181041.0
申请日：2012-08-20
申请人： APPLE INC.
发明人： Meir, Avraham , Baum, Barak , Sommer, Naftali
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/56 , G11C16/26
CPC分类号： G06F11/1008 , G11C7/06 , G11C8/08 , G11C8/12 , G11C11/4091 , G11C11/5642 , G11C13/004 , G11C13/0061 , G11C16/26 , G11C16/349 , G11C27/005 , G11C29/00 , G11C29/021 , G11C29/028 , G11C2211/5641
摘要： A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations.
摘要翻译：一种用于数据存储的方法包括通过将相应的存储值写入组中的存储器单元来将数据存储在一组模拟存储器单元中。使用以第一感测时间感测存储器单元的第一读出操作来读取组中的一个或多个存储器单元。使用比第一感测时间长的第二感测时间来感测存储器单元的第二读出操作来读取组中的至少一个存储器单元。基于第一和第二读出操作的读出结果重建存储在存储单元组中的数据。

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