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1. 发明公开

EP1764703A1 A system for providing access to multiple data buffers of a data retaining and processing device 有权
标题翻译：系统，用于对设备的访问的多个数据缓冲器，用于保持和处理数据的
公开(公告)号：EP1764703A1
公开(公告)日：2007-03-21
申请号：EP06119735.6
申请日：2006-08-29
申请人： STMicroelectronics Pvl. Ltd.
发明人： Isani, Soniya T. , Radhakrishnan, Hariharasudhan Kalayamputhur
IPC分类号： G06F13/28 , G06F13/42
CPC分类号： G06F13/4291 , G06F13/28 , G06F2213/0016
摘要： The present invention provides an area efficient system for providing serial access of multiple data buffers to a data retaining and processing device, comprising a signal synchronization and detection means for synchronizing a clock signal and a data signal, a shifting means for receiving and retaining data received from said data bus to thereby generate a status signal indicating the receipt of data; a reference bus address and said data bus. A comparing means is also provided for comparing said reference bus address with the content of said storage means for generating an address matching signal and a control signal generation means for generating control signals to govern the data write signal generation for said shifting means.
A sequencing means for reading data from said data retaining and processing device and a direct storage access (DMA) controlling means for generating interrupt signals, access request signals.
摘要翻译：本发明提供了到区域有效的系统，用于提供多个数据缓冲器的串行存取的数据保持和处理装置，包括一信号的同步和检测装置，用于同步的时钟信号和数据信号，一个移动装置，用于接收和保持接收到的数据从所述总线的数据，从而生成指示接收数据的状态信号; 参考总线地址和数据总线说。因此，一个比较装置被提供用于与存储所述部件的在地址匹配信号生成的内容和控制信号生成装置，用于产生控制信号，以支配所述数据写入信号生成用于所述移动装置进行比较，所述参考总线地址。测序装置，用于从所述数据保持和处理装置和控制装置，用于产生中断信号时，访问请求信号直接存储存取（DMA）读取数据。

2. 发明公开

EP1756711A1 A METHOD FOR REMOTELY UPGRADING THE FIRMWARE OF A TARGET DEVICE USING WIRELESS TECHNOLOGY 审中-公开
标题翻译：方法对于远程升级固件无线技术的目标设备
公开(公告)号：EP1756711A1
公开(公告)日：2007-02-28
申请号：EP05754554.3
申请日：2005-05-31
申请人： STMicroelectronics Pvl. Ltd.
发明人： SUBBAKRISHNA, S. M. , GUPTA, Naresh, Kumar , KASHIVASI, Mohan
IPC分类号： G06F9/445
CPC分类号： G06F8/65
摘要： The present invention provides a system and method for remotely upgrading the firmware of a target device using wireless technology from the Bluetooth-enabled PC or Laptop to another Bluetooth device e.g. mouse, Keyboard, headset, mobile phone etc. The existing solutions either do not have upgrade capabilities, or require the use of proprietary cables. The solution proposed here extends the 'Connecting without cables' concept of Bluetooth to firmware upgrades. The system comprises a host device for sending the firmware required for upgradation; and a target device containing a first code and a second code wherein said first code identifies details of the firmware; and said second code identifies the completion of the download operation when the firmware is successfully downloaded.

3. 发明公开

EP1734537A2 Bitmap analysis system and method for high speed testing of a memory device 审中-公开
标题翻译：位图分析系统和Verfahren zum Hochgeschwindigkeitstesten einer Speichervorrichtung
公开(公告)号：EP1734537A2
公开(公告)日：2006-12-20
申请号：EP06006812.9
申请日：2006-03-31
申请人： STMicroelectronics Pvl. Ltd.
发明人： Dubey, Prashant
IPC分类号： G11C29/56
CPC分类号： G11C29/56 , G11C2029/5604 , G11C2029/5606
摘要： The invention provides a Bitmap analysis system or BMAS for high-speed testing a memory device (30). The system comprises:
a test engine (38) connected to the memory device (30) for generating bitmaps; and
a First-In First-Out, or FIFO block (31) having a write terminal connected to the test engine (38) and a read terminal connected to a tester (39);

wherein
the memory device (30) is partitioned into small equal sized memory segments;
the FIFO block (31) contains at least one FIFO segment equivalent to the size of said memory segments; and
the test engine (38) sequentially generates and verifies the bitmaps of each of the memory segment.
摘要翻译：本发明提供了一种用于高速测试存储器件（30）的位图分析系统或BMAS。该系统包括：连接到存储器装置（30）的用于产生位图的测试引擎（38）和具有连接到测试引擎（38）的写入终端和连接到测试器（39）的读取终端的先进先出或先进先出（FIFO）块（31）。其中所述存储器件（30）被划分成小的相等尺寸的存储器段; FIFO块（31）包含至少一个等于所述存储器段大小的FIFO段; 并且测试引擎（38）顺序地产生和验证每个存储器段的位图。

4. 发明公开

EP1732082A2 A memory architecture with BIST 审中-公开
标题翻译： Speicherarchitektur mit BIST
公开(公告)号：EP1732082A2
公开(公告)日：2006-12-13
申请号：EP06011188.7
申请日：2006-05-31
申请人： STMicroelectronics Pvl. Ltd.
发明人： Dubey, Prashant
IPC分类号： G11C29/04
CPC分类号： G11C29/12015 , G11C29/003 , G11C29/1201 , G11C29/20 , G11C29/40 , G11C2029/0405 , G11C2029/3602
摘要： This invention relates to a memory architecture with built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. A method for in-built testing of a memory architecture is also described.
摘要翻译：本发明涉及一种具有集成在所述存储器中的内置测试机制的存储器架构，以在面积和速度方面大大减少开销，在随机存取存储器（RAM）中支持非常有效的内置自检。还描述了用于存储器架构的内置测试的方法。

5. 发明公开

EP1771007A3 A video decoder having efficient implementation of reverse variable length decoding 审中-公开
标题翻译：用高效实现视频解码器反向可变长度的数据的解码
公开(公告)号：EP1771007A3
公开(公告)日：2008-07-23
申请号：EP06020701.6
申请日：2006-10-02
申请人： STMicroelectronics Pvl. Ltd.
发明人： Shukla, Mahesh Narain , Taur, Dipti Rani
IPC分类号： H04N7/26 , H04N7/64
CPC分类号： H04N19/69 , H04N19/426 , H04N19/44 , H04N19/61 , H04N19/895 , H04N19/91
摘要： The invention relates to a video decoder comprising:
- a header decoder (110) receiving an encoded bit stream (100);
- a variable length decoder (120) connected to the header decoder (110) and receiving therefrom header decoded data;
- a quantizer and compensator (130) connected to the variable length decoder (120) during backward decoding for performing inverse quantization, transformation and motion compensation of the variable length decoded data and
- an output buffer (140) connected to the quantizer and compensator (130) for storing complete decoded data;

wherein while backward decoding the variable length decoding, inverse quantization, transformation and motion compensation of said header decoded data is done consecutively to obtain complete decoded data till a first point in the backward direction such that said first point is either an error point or a point before an end point of the macroblock containing error detected in the forward direction thereby eliminating the use of intermediate buffer for storing variable length decoded data during backward decoding and reducing the number of computations.

6. 发明公开

EP1732082A3 A memory architecture with BIST 审中-公开
标题翻译：内存架构BIST
公开(公告)号：EP1732082A3
公开(公告)日：2007-11-21
申请号：EP06011188.7
申请日：2006-05-31
申请人： STMicroelectronics Pvl. Ltd.
发明人： Dubey, Prashant
IPC分类号： G11C29/04
CPC分类号： G11C29/12015 , G11C29/003 , G11C29/1201 , G11C29/20 , G11C29/40 , G11C2029/0405 , G11C2029/3602
摘要： This invention relates to a memory architecture with built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. A method for in-built testing of a memory architecture is also described.

7. 发明公开

EP1734537A3 Bitmap analysis system and method for high speed testing of a memory device 审中-公开
标题翻译：位图分析系统和方法的存储器件的高速检测
公开(公告)号：EP1734537A3
公开(公告)日：2007-04-18
申请号：EP06006812.9
申请日：2006-03-31
申请人： STMicroelectronics Pvl. Ltd.
发明人： Dubey, Prashant
IPC分类号： G11C29/56
CPC分类号： G11C29/56 , G11C2029/5604 , G11C2029/5606
摘要： The invention provides a Bitmap analysis system or BMAS for high-speed testing a memory device (30). The system comprises:
a test engine (38) connected to the memory device (30) for generating bitmaps; and
a First-In First-Out, or FIFO block (31) having a write terminal connected to the test engine (38) and a read terminal connected to a tester (39);

wherein
the memory device (30) is partitioned into small equal sized memory segments;
the FIFO block (31) contains at least one FIFO segment equivalent to the size of said memory segments; and
the test engine (38) sequentially generates and verifies the bitmaps of each of the memory segment.

8. 发明公开

EP1771007A2 A video decoder having efficient implementation of reverse variable length decoding 审中-公开
标题翻译：用高效实现视频解码器反向可变长度的数据的解码
公开(公告)号：EP1771007A2
公开(公告)日：2007-04-04
申请号：EP06020701.6
申请日：2006-10-02
申请人： STMicroelectronics Pvl. Ltd.
发明人： Shukla, Mahesh Narain , Taur, Dipti Rani
IPC分类号： H04N7/26
CPC分类号： H04N19/69 , H04N19/426 , H04N19/44 , H04N19/61 , H04N19/895 , H04N19/91
摘要： The invention relates to a video decoder comprising:
- a header decoder (110) receiving an encoded bit stream (100);
- a variable length decoder (120) connected to the header decoder (110) and receiving therefrom header decoded data;
- a quantizer and compensator (130) connected to the variable length decoder (120) during backward decoding for performing inverse quantization, transformation and motion compensation of the variable length decoded data and
- an output buffer (140) connected to the quantizer and compensator (130) for storing complete decoded data;

wherein while backward decoding the variable length decoding, inverse quantization, transformation and motion compensation of said header decoded data is done consecutively to obtain complete decoded data till a first point in the backward direction such that said first point is either an error point or a point before an end point of the macroblock containing error detected in the forward direction thereby eliminating the use of intermediate buffer for storing variable length decoded data during backward decoding and reducing the number of computations.
摘要翻译：本发明涉及视频解码器，包括： - 接收在编码比特流（100）中的报头解码器（110）; - 连接到标头解码器（110）的可变长度解码器（120）和接收从那里头解码的数据; - 连接到反向译码期间的可变长度解码器（120），用于执行逆量化，变换和可变长度的运动补偿的量化器和补偿器（130）解码后的数据和 - 连接到所述量化器和补偿器输出缓冲器（140）（ 130），用于存储完整的解码的数据; worin而向后解码所述报头的可变长度解码，反量化，变换和运动补偿解码数据被连续进行，以获得完整的解码后的数据，直到在向后方向求的第一点即说是罗克韦尔FirstPoint无论错误点或点的向后解码，并减少计算的次数之前，期间在正向方向，从而消除了使用中间缓冲器的，用于存储可变长度检测到的宏块包含错误的结束点的解码数据。

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