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1. 发明公开

EP1284498A3 System and method to screen defect related reliability failures in CMOS SRAMS 审中-公开
标题翻译：系统和方法，用于在CMOS SRAM中分离出误差相关的可靠性失效
公开(公告)号：EP1284498A3
公开(公告)日：2009-12-30
申请号：EP02255731.8
申请日：2002-08-16
申请人： Broadcom Corporation
发明人： Bhattacharya, Surya , Chen, Ming , Shiau, Guang-Jye , Tsau, Liming , Chen, Henry
IPC分类号： H01L21/66 , G11C29/00
CPC分类号： G11C29/025 , G01R31/024 , G01R31/2853 , G01R31/2855 , G11C11/41 , G11C29/006 , G11C29/02
摘要： A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

2. 发明授权

EP1431771B1 Probeless testing of pad buffers on a wafer 失效
标题翻译：一个晶片上的终端缓冲器的非接触式测试
公开(公告)号：EP1431771B1
公开(公告)日：2008-12-31
申请号：EP04100986.1
申请日：1998-03-26
申请人： Texas Instruments Incorporated
发明人： Whetsel, Lee D
IPC分类号： G06F11/267 , G01R31/3185
CPC分类号： G11C29/022 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G01R31/318533 , G11C29/006 , G11C29/48 , G11C2029/3202

3. 发明公开

EP0953986A3 Anordnung zum Testen mehrerer Speicherchips auf einem Wafer 审中-公开
标题翻译：用于测试晶片上的多个存储器芯片的布置
公开(公告)号：EP0953986A3
公开(公告)日：2005-05-11
申请号：EP99105689.6
申请日：1999-03-19
申请人： Infineon Technologies AG
发明人： Haerle, Dieter , Heyne, Patrick , Buck, Martin
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C29/26 , G11C29/48 , G11C29/56
摘要： Die Erfindung betrifft eine Anordnung zum Testen mehrerer Speicherchips (1) auf einem Wafer, bei der unter Verwendung von Nadeln (6) den Speicherchips (1) Versorgungsspannungen (VDD, VSS), ein Initialisierungssignal (I), ein Auslesesignal (CS), ein Taktsignal (CLK) sowie Adressen-, Daten- und Steuersignale zugeführt sind. Die Adressen-, Daten- und Steuersignale werden dabei von einer im Kerf (2) des Speicherchips angeordneten Logik (5) erzeugt und den Speicherchips (1) direkt zugeführt.

4. 发明授权

EP0867727B1 Probeless testing of pad buffers on a wafer 失效
标题翻译：一个晶片上的终端缓冲器的非接触式测试
公开(公告)号：EP0867727B1
公开(公告)日：2004-06-02
申请号：EP98200962.3
申请日：1998-03-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Whetsel, Lee D.
IPC分类号： G01R31/265 , G06F11/267 , G01R31/3185
CPC分类号： G11C29/022 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G01R31/318533 , G01R31/318572 , G11C29/006 , G11C29/48 , G11C2029/3202

5. 发明公开

EP1367597A1 Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method 有权
标题翻译：用于测量在非易失性存储器的非接触式门距离测试结构和相关联的测试程序
公开(公告)号：EP1367597A1
公开(公告)日：2003-12-03
申请号：EP02425360.1
申请日：2002-05-31
申请人： STMicroelectronics S.r.l.
发明人： Camerlenghi, Emilio , Cappelletti, Paolo , Ghilardi, Tecla , Sali, Mauro , Servalli, Giorgio
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C16/04 , G11C29/02 , G11C29/50 , G11C2029/5002
摘要： The present invention relates to an improved integrated non-volatile memory device including a matrix of cells organised into rows, or word lines, and columns, or bit lines, and including corresponding row and column decoding circuits as well as read, modify and erase circuits for reading and modifying data stored in the memory cells. Advantageously, the integrated memory device comprises test structure (2) including a smaller second matrix (3) of cells comprising couples of word lines (WL) each having a difference contact to gate distance.
Each couple of word lines is gradually misaligned from each adjacent couple of word lines by a distance that is variable from couple to couple.
This proposed structure allows monitoring with a large statistic one of the most critical technology parameter for FLASH reliability.
摘要翻译：本发明涉及改进的集成的非易失性存储器装置，其包括组织为行的细胞，或字线，和列，或位线，的一个矩阵和包括对应的行和列解码电路以及读，修改和擦除电路用于读取和修改存储在所述存储器单元中的数据。有利地，所述集成的存储器装置包括测试结构（2）包括包含细胞的字线（WL）每一个都具有差接触到栅极距离耦合的较小的第二矩阵（3）。每一对字线被从每个相邻的一对字线的距离逐渐错开确实是从耦合到耦合变量。此提议的结构允许具有大统计量技术FLASH可靠性的最关键参数之一的监测。

6. 发明公开

EP1350254A2 METHOD FOR READING SEMICONDUCTOR DIE INFORMATION IN A PARALLEL TEST AND BURN-IN SYSTEM 有权
标题翻译：方法用于读取半导体WAFFERN的信息在并行测试和烘烤系统
公开(公告)号：EP1350254A2
公开(公告)日：2003-10-08
申请号：EP01985533.7
申请日：2001-12-04
申请人： Infineon Technologies Richmond, LP
发明人： WHITE, Keith Jordan , EUBANKS, Mark Daniel
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C29/006 , H01L2223/5444
摘要： The present invention defines the number of chip ID fuses (108). A test mode is invoked for the particular chip design being tested causing the chips to output their chip ID's (109). The chip ID is output sequentially until all fuses have been sampled. A first chip ID bit (for each chip being tested) is sampled from the serial output and compared to an expected data (110). The resulting information is interpreted (as above) as a pass or a fail and is stored in a database (112). The method is looped so that each fuse in the chip ID is strobed (114), the interpreted pass/fail results form a binary string. The pass/fail data string (binary chip ID) is loaded into a database.

7. 发明公开

EP1233444A3 Membrane dielectric isolation ic fabrication 失效
标题翻译： Herstellung integrierter Schaltungen auf einer isolierenden Dielektrimembran
公开(公告)号：EP1233444A3
公开(公告)日：2002-12-11
申请号：EP02009643.4
申请日：1993-04-02
申请人： LEEDY, Glenn J.
发明人： LEEDY, Glenn J.
IPC分类号： H01L25/065 , H01L21/60
CPC分类号： H01L25/50 , G02F1/13452 , G02F2001/136281 , G03F7/70658 , G11C29/006 , H01L21/762 , H01L21/76264 , H01L21/76289 , H01L21/764 , H01L21/8221 , H01L23/481 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L23/5387 , H01L25/0652 , H01L25/0655 , H01L27/0207 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/16225 , H01L2224/16227 , H01L2924/00011 , H01L2924/0002 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/3011 , H01L2924/3025 , Y10S148/135 , Y10S438/928 , Y10S438/938 , Y10S438/942 , Y10S438/967 , Y10S438/977 , Y10T29/49128 , Y10T29/49162 , Y10T29/49165 , Y10T29/49171 , Y10T29/4921 , H01L2924/00 , H01L2224/05552 , H01L2224/80001
摘要： General purpose methods for the fabrication of integrated circuits (24, 26, 28, ... 30) from flexible membranes (20, 36) formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor device (24, 26, 28, ... 30) are formed in a semiconductor layer of the membrane (36). The semiconductor membrane layer (36) is initially formed from a substrate (18) of standard thickness, and all but a thin surface layer of substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane which is then packaged as a multichip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D 1C fabrication.
摘要翻译：从由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜（20,36）制造集成电路（24,26,28，... 30）的通用方法。半导体器件（24,26,28，... 30）形成在膜（36）的半导体层中。半导体膜层（36）最初由标准厚度的衬底（18）形成，然后将衬底的薄表面层全部蚀刻或抛光。在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D 1C制造的（电路）膜处理。

8. 发明授权

EP0557079B1 Discretionary lithography for integrated circuits 失效
标题翻译：根据需要为集成电路光刻
公开(公告)号：EP0557079B1
公开(公告)日：1998-12-23
申请号：EP93301161.1
申请日：1993-02-17
申请人： Elm Technology Corporation
发明人： Leedy, Glenn J.
IPC分类号： G06F11/20 , H01L23/525 , H01L21/66
CPC分类号： G03F7/70466 , G11C29/006 , H01L22/22 , H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： Large scale integrated circuits are fabricated using redundant circuit elements to replace defective circuit elements by discretionary interconnect changes as determined by fine-grain testing of the integrated circuits after the logic units (such as individual transistors or logic gates) are fabricated and before they are electrically interconnected. The redundant circuit elements are then interconnected to non-defective circuit elements by one of two methods. In the first method a stepper-scanner apparatus modified to expose most of a resist layer defines the interconnect circuitry, but is shuttered-off over the discretionary interconnect changes. Then the discretionary interconnect changes are exposed by a conventional direct write on wafer pattern generation apparatus. In the second method, the interconnect patterning is accomplished by first fabricating a fixed custom mask defining the interconnect layer for a particular lot size (such as 100) of wafers. The fixed mask is fabricated after each wafer of the lot has been tested, and incorporates all the discretionary changes required to avoid interconnection to each defective circuit element in each of the wafers. The fixed custom mask is then used to expose the resist layer defining the interconnect circuitry for each of the 100 wafers.

9. 发明授权

EP0541288B1 Circuit module redundacy architecture 失效
标题翻译：冗余架构电路模块
公开(公告)号：EP0541288B1
公开(公告)日：1998-07-08
申请号：EP92309866.9
申请日：1992-10-28
申请人： Hsu, Fu-Chieh , Leung, Wingyu
发明人： Hsu, Fu-Chieh , Leung, Wingyu
IPC分类号： G06F11/20
CPC分类号： G11C29/832 , G06F11/2028 , G06F11/2051 , G06F12/0661 , G06F13/4077 , G11C29/006 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/88 , H01L22/22 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

10. 发明授权

EP0366702B1 INTEGRATED CIRCUITS 失效
标题翻译：集成电路。
公开(公告)号：EP0366702B1
公开(公告)日：1994-01-19
申请号：EP88905982.0
申请日：1988-07-15
申请人： CATT, Ivor
发明人： CATT, Ivor
IPC分类号： G06F11/20 , G06F11/26
CPC分类号： G01R31/318511 , G01R31/318505 , G11C29/006
摘要： PCT No. PCT/GB88/00570 Sec. 371 Date Jan. 16, 1990 Sec. 102(e) Date Jan. 16, 1990 PCT Filed Jul. 15, 1988 PCT Pub. No. WO89/00728 PCT Pub. Date Jan. 26, 1989.Each component circuit of an LSI wafer includes a kernel logic section that checks the integrity of the circuit to which it belongs according to a step-by-step process by which progressively larger portions of the circuit are tested. Logic tested during one step is involved in the next step, and once testing of the component circuit is completed, it is extended to testing adjacent circuits of the wafer. Detection of a fault at any stage results in isolation of the faulty circuit or part of it. Test programs and data are stored in ROM within the component circuit, or are supplied via wires bonded to the wafer, for storage in RAM. On completion of the testing, configuration logic within the circuits interconnects the good circuits in an array for communication of signals between them. The kernel logic may be shared between groups of component circuits.

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