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1. 发明授权

EP2088442B1 PARALLEL TEST CIRCUIT AND METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：并行测试电路和方法半导体器件
公开(公告)号：EP2088442B1
公开(公告)日：2013-01-09
申请号：EP07831134.7
申请日：2007-11-02
申请人： NEC Corporation
发明人： MIZUNO, Masayuki
IPC分类号： G01R31/317 , G11C29/12 , G11C29/26
CPC分类号： G01R31/31703 , G11C29/26 , G11C2029/2602 , G11C2029/4002 , G11C2029/5602

2. 发明公开

EP1860558A3 Method and apparatus for latent fault memory scrub in memory upon which a computer hardware strongly relies 审中-公开
标题翻译：一种用于在存储器中除去潜误差从该计算机硬件强烈依赖的方法和装置
公开(公告)号：EP1860558A3
公开(公告)日：2009-01-21
申请号：EP07108806.6
申请日：2007-05-24
申请人： Honeywell International Inc.
发明人： Thompson, Steven R.
IPC分类号： G06F11/10 , G05B9/03 , G05D1/00 , G06F11/16 , G11C29/36
CPC分类号： G11C29/36 , G06F11/106 , G11C2029/0401 , G11C2029/0409 , G11C2029/4002
摘要： A method for operating a memory checker (100) in a command monitoring architecture comprising at least two processing lanes (102, 104) comprises a first step of receiving a command to activate a first test mode. The first test mode comprises an initial step of inverting data read from a memory (112, 114) and inverting data written to the memory (112, 114). Next, it is determined if there is a match between data associated with a first processing lane (102) and retrieved by a second checker logic (120) associated with a second processing lane (104) and with data associated with a second processing lane (104) and retrieved by a first checker logic (116) associated with the first processing lane (102). A failure in the memory (112, 114) is determined if there is no match.

3. 发明公开

EP1860558A2 Method and apparatus for latent fault memory scrub in memory intensive computer hardware 审中-公开
标题翻译：一种用于在存储器中除去潜误差从该计算机硬件强烈依赖的方法和装置
公开(公告)号：EP1860558A2
公开(公告)日：2007-11-28
申请号：EP07108806.6
申请日：2007-05-24
申请人： Honeywell International Inc.
发明人： Thompson, Steven R.
IPC分类号： G06F11/10
CPC分类号： G11C29/36 , G06F11/106 , G11C2029/0401 , G11C2029/0409 , G11C2029/4002
摘要： A method for operating a memory checker (100) in a command monitoring architecture comprising at least two processing lanes (102, 104) comprises a first step of receiving a command to activate a first test mode. The first test mode comprises an initial step of inverting data read from a memory (112, 114) and inverting data written to the memory (112, 114). Next, it is determined if there is a match between data associated with a first processing lane (102) and retrieved by a second checker logic (120) associated with a second processing lane (104) and with data associated with a second processing lane (104) and retrieved by a first checker logic (116) associated with the first processing lane (102). A failure in the memory (112, 114) is determined if there is no match.
摘要翻译：一种用于在命令监视体系结构包括至少两个处理通道（102，104）操作存储器检验器（100）方法包括：接收命令，以激活第一测试模式的第一步骤。第一测试模式反转从存储器（112，114）读出的数据和反相写入到存储器（112，114）的数据的初始步骤的包括。接着，它是确定的开采，如果有通过与第二处理通道（104）中并用（与第二处理通道相关联的数据相关联的第二检查器逻辑（120）与第一处理通道（102）相关联，并且检索到的数据之间的匹配 104），并通过与所述第一处理通道（102）相关联的第一检查器逻辑（116）检索。如果不存在匹配在存储器（112，114）的故障被确定。

4. 发明公开

EP1831892A4 SYSTEM FOR PERFORMING FAST TESTING DURING FLASH REFERENCE CELL SETTING 审中-公开
标题翻译： SYSTEM FOR执行快速试验FLASH参考单元设置期间
公开(公告)号：EP1831892A4
公开(公告)日：2009-06-10
申请号：EP05848820
申请日：2005-11-18
申请人： ATMEL CORP
发明人： BEDARIDA LORENZO , BARTOLI SIMONE , SURICO STEFANO , FRULIO MASSIMILIANO
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C16/04 , G11C16/28 , G11C29/24 , G11C29/50004 , G11C2029/4002
摘要： An embedded circuit (14) in a memory device (10) is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells (20). An external test device (16) programs at least one reference cell (22) to a predetermined value. The embedded circuit uses the cell (22) programmed by the external device as a comparative reference to program additional reference cells (20).

5. 发明公开

EP1831892A1 SYSTEM FOR PERFORMING FAST TESTING DURING FLASH REFERENCE CELL SETTING 审中-公开
标题翻译： SYSTEM FOR执行快速试验FLASH参考单元设置期间
公开(公告)号：EP1831892A1
公开(公告)日：2007-09-12
申请号：EP05848820.6
申请日：2005-11-18
申请人： ATMEL CORPORATION
发明人： BEDARIDA, Lorenzo , BARTOLI, Simone , SURICO, Stefano , FRULIO, Massimiliano
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C16/04 , G11C16/28 , G11C29/24 , G11C29/50004 , G11C2029/4002
摘要： An embedded circuit (14) in a memory device (10) is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells (20). An external test device (16) programs at least one reference cell (22) to a predetermined value. The embedded circuit uses the cell (22) programmed by the external device as a comparative reference to program additional reference cells (20).

6. 发明公开

EP3226246A1 METHOD AND SYSTEM FOR PREDICTING HIGH-TEMPERATURE OPERATING LIFE OF SRAM DEVICES 审中-公开
标题翻译：用于预测SRAM器件的高温工作寿命的方法和系统
公开(公告)号：EP3226246A1
公开(公告)日：2017-10-04
申请号：EP17162508.0
申请日：2017-03-23
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： CHIEN, Wei Ting , ZHU, Yue Qin , SONG, Yongliang , ZHAO, Yong
IPC分类号： G11C29/00 , G11C29/06 , G11C29/50 , G11C29/56 , G01R31/26 , G01R31/28 , G11C7/04 , G11C11/412
CPC分类号： G01R31/2875 , G01R31/2628 , G01R31/2642 , G01R31/2851 , G11C11/412 , G11C29/006 , G11C29/06 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C29/56008 , G11C2029/0403 , G11C2029/4002
摘要： A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.
摘要翻译：一种用于预测集成电路（IC）的高温工作寿命的方法包括在IC的器件上执行偏置温度不稳定性测试和高温工作寿命测试，建立器件偏置温度不稳定性与IC的高温工作寿命之间的关系，基于偏置温度不稳定性测试和高温工作寿命测试的结果的温度工作寿命。该方法还包括提供大量后续集成电路（IC），在IC的器件上执行晶片级偏置温度不稳定性测试，并且基于晶片级偏置的结果预测IC的高温工作寿命温度不稳定性测试，并基于器件偏置温度不稳定性与IC的高温工作寿命之间建立的关系。与传统方法相比，该方法可以节省大量的精力和时间，以精确预测IC的高温工作寿命。

7. 发明公开

EP2088442A4 PARALLEL TEST CIRCUIT AND METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：并行测试电路和方法半导体器件
公开(公告)号：EP2088442A4
公开(公告)日：2011-06-22
申请号：EP07831134
申请日：2007-11-02
申请人： NEC CORP
发明人： MIZUNO MASAYUKI
IPC分类号： G11C29/12 , G01R31/317
CPC分类号： G01R31/31703 , G11C29/26 , G11C2029/2602 , G11C2029/4002 , G11C2029/5602

8. 发明公开

EP2088442A1 PARALLEL TEST CIRCUIT AND METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：巴勒斯坦公民组织（UNDERLEL-PRÜFSCHALTUNGUND VERFAHREN UND HALBLEITERANORDNUNG）
公开(公告)号：EP2088442A1
公开(公告)日：2009-08-12
申请号：EP07831134.7
申请日：2007-11-02
申请人： NEC Corporation
发明人： MIZUNO, Masayuki
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G11C29/26 , G11C2029/2602 , G11C2029/4002 , G11C2029/5602
摘要： A test circuit and a test method, in which the number of input/output ports needed for testing is not increased even if the number of devices under test, subjected to parallel testing, is increased. The test circuit includes a first transfer circuit, a second transfer circuit and comparators 14-1, 14-2 and so on, and performs parallel testing of a plurality of chips under test 10-1, 10-2, 10-3 and so on. The first transfer circuit includes flip-flops 11-1, 11-2, 11-3 and so on. A data pattern from a tester 1 is supplied to the initial stage chip under test 10-1. To the remaining chips under test 10-2, 10-3 and so on, output data from the corresponding stages of the first transfer circuit are supplied. The second transfer circuit sequentially transfers an output of the initial stage chip under test 10-1, as an expected value pattern, in response to clock cycles. The comparator compares output data of the chip under test with an expected value pattern from the corresponding stage of the second transfer circuit.
摘要翻译：测试电路和测试方法，其中即使受到并行测试的受测设备的数量增加，测试所需的输入/输出端口的数量也不会增加。测试电路包括第一传输电路，第二传输电路和比较器14-1,14-2等，并且对被测试的多个芯片10-1,10-2,10-3等进行并行测试上。第一传送电路包括触发器11-1,11-2,11-3等。来自测试器1的数据模式被提供给被测试的初始级芯片10-1。对于被测试的其余芯片10-2,10-3等，提供来自第一传送电路的相应级的输出数据。第二传输电路响应于时钟周期顺序地将待测试的初始级芯片的输出作为期望值模式传送。比较器将待测芯片的输出数据与来自第二传输电路的相应级的期望值模式进行比较。

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