专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP2624302A1 Trench power MOSFET 审中-公开
标题翻译：沟槽Leistungs-MOSFET
公开(公告)号：EP2624302A1
公开(公告)日：2013-08-07
申请号：EP13154655.8
申请日：2004-03-04
申请人： Advanced Analogic Technologies, Inc. , Advanced Analogic Technologies (Hong Kong) Limited
发明人： Williams, Richard K. , Cornell, Michael E. , Chan, Wai Tien
IPC分类号： H01L29/78 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66734 , H01L29/7811
摘要： Power MOSFET's and fabrication processes for power MOSFET's use a continuous conductive gate structure within trenches to avoid device topology problems caused when a gate bus extends above a substrate. The conductive gate structure forms trench gates in an active device region and forms a gate bus in a gate bus trench. The gate bus trench connects to device trenches and can be wide to facilitate forming a contact to the gate bus. The device trenches can be narrow to maximize device density. The gate bus and/or gates contain a metal/silicide to reduce resistance, and polysilicon surrounds the metal/silicide to prevent metal atoms from penetrating the gate oxide layers. A CMP process can planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with forming self-aligned or conventional contacts in the active device region.
摘要翻译：功率MOSFET和功率MOSFET的制造工艺在沟槽内使用连续的导电栅极结构，以避免栅极总线延伸到衬底上方引起的器件拓扑问题。导电栅极结构在有源器件区域中形成沟槽栅极，并在栅极总线沟槽中形成栅极总线。栅极总线沟槽连接到器件沟槽，并且可以宽以便于形成与栅极总线的接触。器件沟槽可以窄到最大化器件密度。栅极总线和/或栅极包含金属/硅化物以降低电阻，并且多晶硅围绕金属/硅化物以防止金属原子穿过栅极氧化物层。 CMP工艺可以平坦化导电栅极结构和/或覆盖绝缘层。该过程与在有源器件区域中形成自对准或常规触点相容。

2. 发明公开

EP2290695A1 Trench-constrained isolation diffusion in a semiconductor material 审中-公开
标题翻译： Grabenbegrenzte扩散zur隔离在einem Halbleitermaterial
公开(公告)号：EP2290695A1
公开(公告)日：2011-03-02
申请号：EP10189464.0
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： Williams, Richard K. , Cornell, Michael , Chan, Wai Tien
IPC分类号： H01L29/00 , H01L27/095
CPC分类号： H01L27/0826 , H01L21/8224 , H01L21/82285 , H01L27/0821 , H01L29/6625 , H01L29/66272 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a pair of trenches (408A,408B) filled with a dielectric material (406). Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped regions diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer (410) is formed at an interface between an epitaxial layer (402) and a substrate (400), at a location generally below the dopant in the mesa.; When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget.
摘要翻译：半导体衬底包括填充有电介质材料（406）的一对沟槽（408A，408B）。引入到沟槽之间的台面的掺杂剂被限制为当衬底经受热处理时横向扩散。因此，半导体器件可以在衬底上更紧密地间隔开，并且可以增加器件的封装密度。另外，沟槽约束掺杂区域比无约束扩散更快和更深地扩散，从而减少完成所需深度扩散所需的时间和温度。该技术可以用于诸如双极晶体管的半导体器件以及将器件彼此电隔离的隔离区域。在一组实施例中，在外延层（402）和衬底（400）之间的界面处，在台面的通常低于掺杂剂的位置处形成掩埋层（410）。当衬底经受热处理时，掩埋层向上扩散，台面中的掺杂剂向下扩散直到两个掺杂剂合并形成从外延层的表面向埋入层向下延伸的隔离区域或沉降片。在另一个实施例中，掺杂剂以高达几MeV的高能量注入电介质填充的沟槽之间，然后扩散，结合深度注入和沟槽约束扩散的优点，以最小的热预算实现深度扩散。

3. 发明公开

EP1761953A1 TRENCH MOSFET WITH RECESSED CLAMPING DIODE 审中-公开
标题翻译：与凹进钳位二极管的沟槽MOSFET
公开(公告)号：EP1761953A1
公开(公告)日：2007-03-14
申请号：EP04756535.3
申请日：2004-06-30
申请人： Advanced Analogic Technologies, Inc. , Advanced Analogic Technologies (Hong Kong) Limited
发明人： WILLIAMS, Richard , CORNELL, Michael , Chan, Wai Tien
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66734 , H01L29/7808
摘要： In a trench-gated MOSFET (840) including an epitaxial layer (842) over a substrate (841) of like conductivity and trenches containing thick bottom oxide (846), sidewall gate oxide (850), and conductive gates (844), body regions (843) of the complementary conductivity are shallower than the gates (844), and clamp regions (853) are deeper and more heavily doped than the body regions but shallower than the trenches. Zener junctions clamp a drain-source voltage lower than the FPI breakdown of body junctions near the trenches, but the zener junctions, being shallower than the trenches, avoid undue degradation of the maximum drain-source voltage. The epitaxial layer (842) may have a dopant concentration that increases step-wise or continuously with depth. Chained implants of the body (843) and clamp regions (853) permit accurate control of dopant concentrations and of junction depth. Alternative fabrication processes permit implantation of the body (843) and clamp regions (853) before gate bus (852) formation or through the gate bus (852) after gate bus formation.

4. 发明公开

EP2421040A1 A modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology 审中-公开
标题翻译：双极CMOS-DMOS-Analog-Schaltung und Leistungstransistortechnik的Modulare integrierte
公开(公告)号：EP2421040A1
公开(公告)日：2012-02-22
申请号：EP11189604.9
申请日：2003-09-19
申请人： Advanced Analogic Technologies, Inc.
发明人： Williams, Richard K. , Cornell, Michael E. , Chan, Wai Tien
IPC分类号： H01L27/082 , H01L27/088 , H01L27/092 , H01L27/102 , H01L27/105 , H01L21/76 , H01L21/761
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices formed in a semiconductor substrate of a first conductivity type, said substrate not comprising an epitaxial layer, said family comprising a trench-gated MOSFET, said trench-gated MOSFET comprising: at least four trenches formed at a surface of said substrate, a conductive gate material being disposed in each of said trenches, said gate material in each trench being separated from said semiconductor substrate by a dielectric layer, a first trench being separated from a second trench by a first mesa, said second trench being separated from a third trench by a second mesa, and said third trench being separated from a fourth trench by a third mesa; said second mesa comprising: a source region of a second conductivity type opposite to said first conductivity type adjacent a surface of said substrate and extending entirely across said second mesa, said source region having a first doping concentration of said second conductivity type; a body region of said first conductivity type adjacent said source region and extending entirely across said second mesa; and a high voltage drift region adjacent said body region and extending entirely across said second mesa, said high voltage drift region having a second doping concentration of said second conductivity type; each of said first and third mesas comprising: a drain region of said second conductivity adjacent a surface of said substrate and extending entirely across said first and third mesas, respectively, said drain region having a third doping concentration of said second conductivity type; and a well of said second conductivity type adjacent said drain region and extending entirely across said first and third mesas, respectively, said well having a fourth doping concentration of said second conductivity type; and a first layer of said second conductivity type, said first layer abutting a bottom of each of said first and second trenches and said high voltage drift region; a second layer of said second conductivity type, said second layer abutting a bottom of each of said third and fourth trenches and said high voltage drift region, said first layer being spaced apart from said second layer; wherein said first doping concentration is greater than said second doping concentration and said third doping concentration is greater than said fourth doping concentration.
摘要翻译：一种半导体器件，形成在第一导电类型的半导体衬底中，所述衬底不包括外延层，所述族包括沟槽门控MOSFET，所述沟槽门控MOSFET包括：形成在所述第一导电类型的表面的至少四个沟槽衬底，导电栅极材料设置在每个所述沟槽中，每个沟槽中的所述栅极材料通过电介质层与所述半导体衬底分离，第一沟槽通过第一台面与第二沟槽分离，所述第二沟槽被分离从第三沟槽通过第二台面，并且所述第三沟槽与第四沟槽分离第三台面; 所述第二台面包括：与所述衬底的表面相邻并且完全延伸穿过所述第二台面的所述第一导电类型相反的第二导电类型的源极区域，所述源极区域具有所述第二导电类型的第一掺杂浓度; 所述第一导电类型的身体区域与所述源极区域相邻并且完全延伸穿过所述第二台面; 以及与所述体区相邻并且完全延伸穿过所述第二台面的高电压漂移区，所述高电压漂移区具有所述第二导电类型的第二掺杂浓度; 所述第一和第三台面中的每一个包括：所述第二导电体的漏极区域邻近所述衬底的表面并且分别延伸穿过所述第一和第三台面，所述漏极区域具有所述第二导电类型的第三掺杂浓度; 以及与所述漏极区相邻并且分别延伸穿过所述第一和第三台面的所述第二导电类型的阱，所述阱具有所述第二导电类型的第四掺杂浓度; 和所述第二导电类型的第一层，所述第一层邻接所述第一和第二沟槽和所述高电压漂移区域中的每一个的底部; 所述第二导电类型的第二层，所述第二层邻接所述第三和第四沟槽和所述高电压漂移区域中的每一个的底部，所述第一层与所述第二层间隔开; 其中所述第一掺杂浓度大于所述第二掺杂浓度，并且所述第三掺杂浓度大于所述第四掺杂浓度。

5. 发明公开

EP2214198A3 Isolated complementary MOS devices in EPI-less substrate 有权
标题翻译：隔离互补MOS器件在EPI无线类基片
公开(公告)号：EP2214198A3
公开(公告)日：2010-08-18
申请号：EP10158458.9
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： Williams, Richard K. , Cornell, Michael E. , Chan, Wai Tien
IPC分类号： H01L21/30 , H01L21/46 , H01L21/3205 , H01L21/332 , H01L21/336 , H01L21/425 , H01L29/72 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A process of fabricating a semiconductor device is disclosed comprising providing a semiconductor substrate of a first conductivity type, the substrate not containing an epitaxial layer; forming a first mask on a surface of the substrate, said first mask having a first opening defining a location of a first deep layer in a lateral dimension; implanting a dopant of a second conductivity type through the first opening to form the first deep layer; forming a second mask on the surface of the substrate, said second mask having a second opening defining a location of a second deep layer in the lateral dimension, a width of the second opening being less that a width of the first opening; and implanting dopant of the first conductivity type through the second opening to form the second deep layer. The projected range of the implant of dopant of the first conductivity type is less than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends above the first deep layer. Alternatively, the projected range of the implant of dopant of the first conductivity type is greater than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends below the first deep layer.

6. 发明授权

EP2214198B1 Process of fabricating an isolation structure in a semiconductor device 有权
标题翻译：在半导体装置的制造方法，用于隔离结构
公开(公告)号：EP2214198B1
公开(公告)日：2013-04-17
申请号：EP10158458.9
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： Williams, Richard K. , Cornell, Michael E. , Chan, Wai Tien
IPC分类号： H01L21/265 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A process of fabricating a semiconductor device is disclosed comprising providing a semiconductor substrate of a first conductivity type, the substrate not containing an epitaxial layer; forming a first mask on a surface of the substrate, said first mask having a first opening defining a location of a first deep layer in a lateral dimension; implanting a dopant of a second conductivity type through the first opening to form the first deep layer; forming a second mask on the surface of the substrate, said second mask having a second opening defining a location of a second deep layer in the lateral dimension, a width of the second opening being less that a width of the first opening; and implanting dopant of the first conductivity type through the second opening to form the second deep layer. The projected range of the implant of dopant of the first conductivity type is less than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends above the first deep layer. Alternatively, the projected range of the implant of dopant of the first conductivity type is greater than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends below the first deep layer.

7. 发明公开

EP2214198A2 Isolated complementary MOS devices in EPI-less substrate 有权
标题翻译： Herstellungsverfahrenfüreine Isolationsstruktur in einem Halbleiterbauelement
公开(公告)号：EP2214198A2
公开(公告)日：2010-08-04
申请号：EP10158458.9
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： Williams, Richard K. , Cornell, Michael E. , Chan, Wai Tien
IPC分类号： H01L21/30 , H01L21/46 , H01L21/3205 , H01L21/332 , H01L21/336 , H01L21/425 , H01L29/72 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A process of fabricating a semiconductor device is disclosed comprising providing a semiconductor substrate of a first conductivity type, the substrate not containing an epitaxial layer; forming a first mask on a surface of the substrate, said first mask having a first opening defining a location of a first deep layer in a lateral dimension; implanting a dopant of a second conductivity type through the first opening to form the first deep layer; forming a second mask on the surface of the substrate, said second mask having a second opening defining a location of a second deep layer in the lateral dimension, a width of the second opening being less that a width of the first opening; and implanting dopant of the first conductivity type through the second opening to form the second deep layer. The projected range of the implant of dopant of the first conductivity type is less than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends above the first deep layer. Alternatively, the projected range of the implant of dopant of the first conductivity type is greater than the projected range of the implant of dopant of the second conductivity type such that the second deep layer overlaps and extends below the first deep layer.
摘要翻译：公开了制造半导体器件的工艺，其包括提供第一导电类型的半导体衬底，所述衬底不包含外延层; 在所述基板的表面上形成第一掩模，所述第一掩模具有第一开口，所述第一开口限定在横向尺寸上的第一深层的位置; 通过所述第一开口注入第二导电类型的掺杂剂以形成所述第一深层; 在所述基板的表面上形成第二掩模，所述第二掩模具有第二开口，所述第二开口限定所述横向尺寸中的第二深层的位置，所述第二开口的宽度小于所述第一开口的宽度; 以及通过所述第二开口注入所述第一导电类型的掺杂剂以形成所述第二深层。第一导电类型的掺杂剂的注入的投影范围小于第二导电类型的掺杂剂的注入的投影范围，使得第二深层与第一深层之上重叠并延伸。或者，第一导电类型的掺杂剂的注入的投影范围大于第二导电类型的掺杂剂的注入的投影范围，使得第二深层与第一深层之下重叠并延伸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式