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1. 发明公开

EP2290695A1 Trench-constrained isolation diffusion in a semiconductor material 审中-公开
标题翻译： Grabenbegrenzte扩散zur隔离在einem Halbleitermaterial
公开(公告)号：EP2290695A1
公开(公告)日：2011-03-02
申请号：EP10189464.0
申请日：2003-08-13
申请人： Advanced Analogic Technologies, Inc.
发明人： Williams, Richard K. , Cornell, Michael , Chan, Wai Tien
IPC分类号： H01L29/00 , H01L27/095
CPC分类号： H01L27/0826 , H01L21/8224 , H01L21/82285 , H01L27/0821 , H01L29/6625 , H01L29/66272 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a pair of trenches (408A,408B) filled with a dielectric material (406). Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped regions diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer (410) is formed at an interface between an epitaxial layer (402) and a substrate (400), at a location generally below the dopant in the mesa.; When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget.
摘要翻译：半导体衬底包括填充有电介质材料（406）的一对沟槽（408A，408B）。引入到沟槽之间的台面的掺杂剂被限制为当衬底经受热处理时横向扩散。因此，半导体器件可以在衬底上更紧密地间隔开，并且可以增加器件的封装密度。另外，沟槽约束掺杂区域比无约束扩散更快和更深地扩散，从而减少完成所需深度扩散所需的时间和温度。该技术可以用于诸如双极晶体管的半导体器件以及将器件彼此电隔离的隔离区域。在一组实施例中，在外延层（402）和衬底（400）之间的界面处，在台面的通常低于掺杂剂的位置处形成掩埋层（410）。当衬底经受热处理时，掩埋层向上扩散，台面中的掺杂剂向下扩散直到两个掺杂剂合并形成从外延层的表面向埋入层向下延伸的隔离区域或沉降片。在另一个实施例中，掺杂剂以高达几MeV的高能量注入电介质填充的沟槽之间，然后扩散，结合深度注入和沟槽约束扩散的优点，以最小的热预算实现深度扩散。

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