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31. 发明公开

EP3267441A1 THREE-DIMENSIONAL FLASH MEMORY SYSTEM 有权
标题翻译：三维闪存系统
公开(公告)号：EP3267441A1
公开(公告)日：2018-01-10
申请号：EP17184964.9
申请日：2013-10-09
申请人： Silicon Storage Technology Inc.
发明人： Tran, Hieu Van , Nguyen, Hung Quoc , Reiten, Mark
IPC分类号： G11C5/02 , G11C5/06 , G11C16/30 , G11C29/26 , G11C7/04 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/02 , G11C29/12 , G11C29/00 , H01L25/065 , H01L25/18
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了一种三维闪存系统。

32. 发明公开

EP3245673A1 3D INTEGRATED CIRCUIT 审中-公开
标题翻译： 3D集成电路
公开(公告)号：EP3245673A1
公开(公告)日：2017-11-22
申请号：EP15819969.5
申请日：2015-12-10
申请人： Qualcomm Incorporated
发明人： LAW, Oscar , LIU, Chunchen , LU, Ju-Yi
IPC分类号： H01L25/065 , G01R31/00 , G11C29/08 , H01L23/528
CPC分类号： H01L25/0657 , G01R31/318513 , G11C29/1201 , G11C29/48 , H01L22/32 , H01L23/5384 , H01L23/5385 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/0002 , H03K17/002 , H03K17/56 , H01L2924/00
摘要： A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to connect the dies on the different layers. In some aspects, a power distribution network (PDN) is routed from a first layer through the switches to supply power to at least one other layer, thereby reducing routing congestion on the layers. The switches can be placed around the periphery of an IC package to improve heat dissipation (e.g., by improving heat transfer from the center to the edge of the IC package). The switches can be used for routing test signals and/or other signals between layers, thereby improving test functionality and/or fault recovery.

33. 发明授权

EP3029684B1 TEST CIRCUIT AND METHOD FOR CONTROLLING TEST CIRCUIT 有权
公开(公告)号：EP3029684B1
公开(公告)日：2017-09-27
申请号：EP15196814.6
申请日：2015-11-27
申请人： FUJITSU LIMITED
发明人： OSHIYAMA, Gen , SHIKIBU, Takahiro , MORIYAMA, Osamu , YAMAZAKI, Iwao , CHIYONOBU, Akihiro
IPC分类号： G11C29/12 , H01L25/065 , G01R31/3185 , G01R31/3177 , G11C29/32
CPC分类号： G01R31/3177 , G01R31/318505 , G01R31/318513 , G11C29/1201 , G11C29/32 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

34. 发明公开

EP3168746A1 HARDWARE MONITOR TO VERIFY MEMORY UNITS 有权
标题翻译：硬件监视器来验证内存单元
公开(公告)号：EP3168746A1
公开(公告)日：2017-05-17
申请号：EP16198506.4
申请日：2016-11-11
申请人： Imagination Technologies Limited
发明人： DARBARI, Ashish , SINGLETON, Iain
IPC分类号： G06F11/22 , G11C29/00
CPC分类号： G11C29/38 , G06F11/2221 , G06F11/3037 , G06F11/3409 , G11C29/1201 , G11C29/44 , G11C2029/0409
摘要： Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
摘要翻译：硬件监视器可由形式验证工具使用，以彻底验证存储器单元的硬件设计。硬件监视器包括检测逻辑以监视存储器单元的实例的一个或多个控制信号和/或数据信号以检测符号写入和符号读取。在一些例子中，符号写入是将符号数据写入符号地址; 在其他例子中，符号写入是将任何数据写入符号地址。符号读取是对符号地址的读取。硬件监视器还包括断言验证逻辑，其验证断言，读取与符号读取相对应的数据匹配与读取之前的一个或多个符号写入相关联的写入数据。

35. 发明公开

EP2608261A3 Semiconductor device 审中-公开
公开(公告)号：EP2608261A3
公开(公告)日：2017-03-08
申请号：EP12196671.7
申请日：2012-12-12
申请人： PS4 Luxco S.a.r.l.
发明人： Nakazawa, Shigeyuki , Ishikawa, Toru
IPC分类号： H01L25/065 , H01L23/48 , H01L23/58 , G11C5/06 , G11C29/02 , G11C29/12 , H01L21/66
CPC分类号： H01L23/5226 , G11C5/063 , G11C29/025 , G11C29/1201 , H01L22/34 , H01L23/481 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06596
摘要： Disclosed herein is a semiconductor chip that includes:
a plurality of penetration electrodes (15) each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and
a third penetration electrode; and a wiring (18) configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode.

36. 发明公开

EP3087488A1 INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR 有权
标题翻译： DETEKTION UND REPARATUR VON DEFEKTEN IN INTEGRIERTEN SCHALTKREISEN
公开(公告)号：EP3087488A1
公开(公告)日：2016-11-02
申请号：EP14873755.4
申请日：2014-12-22
申请人： Intel Corporation
发明人： QUERBACH, Bruce , SCHOENBORN, Theodore Z. , ZIMMERMAN, David J. , ELLIS, David G. , HAMPSON, Christopher W. , WAN, Ifar , ZHANG, Yulan , MALLELA, Ramakrishna , LUI, William K.
IPC分类号： G06F11/07 , G06F11/263
CPC分类号： G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
摘要： In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.
摘要翻译：根据本说明书，一种装置包括内部缺陷检测和修复电路，其包括内置在该装置内的自检逻辑电路和内置在该装置内的自修复逻辑电路。在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。在识别一个或多个有缺陷的存储器单元时，内建的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。在一个实施例中，作为存储器地址和周期性地址偏移的函数产生数据模式。本文描述了其它方面。

37. 发明公开

EP2834817A1 MEMORY WITH REDUNDANT SENSE AMPLIFIER 审中-公开
标题翻译： SPEICHER MIT EINEM REDUNDANTENERFASSUNGSVERSTÄRKER
公开(公告)号：EP2834817A1
公开(公告)日：2015-02-11
申请号：EP13717609.5
申请日：2013-03-25
申请人： Apple Inc.
发明人： SENINGEN, Michael R. , RUNAS, Michael E.
IPC分类号： G11C29/12 , G11C29/50
CPC分类号： G11C11/418 , G11C7/06 , G11C7/1051 , G11C29/1201 , G11C29/50 , G11C29/50016 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
摘要翻译：公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。第一读出放大器的增益电平可以高于第二读出放大器的增益电平。输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出能够被设置为高阻抗状态。

38. 发明公开

EP1830366A4 BIAS APPLICATION METHOD OF STORAGE AND STORAGE 有权
标题翻译： BIAS应用程序存储和存储
公开(公告)号：EP1830366A4
公开(公告)日：2009-11-11
申请号：EP04807686
申请日：2004-12-24
申请人： SPANSION JAPAN LTD , SPANSION LLC
发明人： FURUYAMA TAKAAKI , KATO KENTA
IPC分类号： G11C29/00 , G11C16/02
CPC分类号： G11C29/1201 , G11C5/14 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/50004 , G11C29/82 , G11C2029/5006

39. 发明公开

EP1825479A4 PROGRAMMABLE MEMORY BUILT-IN-SELF-TEST (MBIST) METHOD AND APPARATUS 审中-公开
标题翻译：方法和设备为一体的综合可编程存储器自测试（MBIST）
公开(公告)号：EP1825479A4
公开(公告)日：2008-04-16
申请号：EP05849415
申请日：2005-11-18
申请人： MENTOR GRAPHICS CORP
发明人： MUKHERJEE NILANJAN , DU XIAOGANG , CHENG WU-TUNG
IPC分类号： G11C29/00
CPC分类号： G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要： Programmable memory built-in-self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

40. 发明公开

EP1825479A2 PROGRAMMABLE MEMORY BUILT-IN-SELF-TEST (MBIST) METHOD AND APPARATUS 审中-公开
标题翻译：方法和设备为一体的综合可编程存储器自测试（MBIST）
公开(公告)号：EP1825479A2
公开(公告)日：2007-08-29
申请号：EP05849415.4
申请日：2005-11-18
申请人： Mentor Graphics Corporation
发明人： MUKHERJEE, Nilanjan , DU, Xiaogang , CHENG, Wu-tung
IPC分类号： G11C29/00
CPC分类号： G01R31/3187 , G01R31/31724 , G01R31/318519 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/20 , G11C2029/0401 , G11C2029/0405 , G11C2029/3602 , G11C2029/5604
摘要： Programmable memory built-in-self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

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