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1. 发明授权

EP3037833B1 TEST CIRCUIT AND METHOD OF CONTROLLING TEST CIRCUIT 有权
公开(公告)号：EP3037833B1
公开(公告)日：2019-11-13
申请号：EP15192467.7
申请日：2015-10-30
申请人： FUJITSU LIMITED
发明人： OSHIYAMA, Gen , MORIYAMA, Osamu , SHIKIBU, Takahiro , CHIYONOBU, Akihiro , YAMAZAKI, Iwao
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/317

2. 发明公开

EP3029684A1 TEST CIRCUIT AND METHOD FOR CONTROLLING TEST CIRCUIT 有权
标题翻译：测试电路和控制测试电路的方法
公开(公告)号：EP3029684A1
公开(公告)日：2016-06-08
申请号：EP15196814.6
申请日：2015-11-27
申请人： FUJITSU LIMITED
发明人： OSHIYAMA, Gen , SHIKIBU, Takahiro , MORIYAMA, Osamu , YAMAZAKI, Iwao , CHIYONOBU, Akihiro
IPC分类号： G11C29/12 , H01L25/065 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318505 , G01R31/318513 , G11C29/1201 , G11C29/32 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.
摘要翻译：一种用于测试包括半导体芯片的半导体器件的测试电路，包括：测试输入端子，被配置为接收用于测试半导体器件的数据; 在半导体芯片中的一个半导体芯片和半导体芯片中的另一半导体芯片之间提供的信号路径，提供给测试输入端的数据通过信号路径传输; 选择信号发生器，被提供在所述一个半导体芯片中并且经由所述信号路径耦合到所述另一个半导体芯片，被配置为当经由所述信号路径中的一个或多个信号路径接收到指示期望值的数据时，产生指示所述一个或更多的信号路径; 以及路径选择器，被提供在所述至少一个半导体芯片中并且被耦合到所述信号路径，被配置为基于所述选择信号来选择在测试所述半导体器件时要使用的信号路径。

3. 发明授权

EP3029684B1 TEST CIRCUIT AND METHOD FOR CONTROLLING TEST CIRCUIT 有权
公开(公告)号：EP3029684B1
公开(公告)日：2017-09-27
申请号：EP15196814.6
申请日：2015-11-27
申请人： FUJITSU LIMITED
发明人： OSHIYAMA, Gen , SHIKIBU, Takahiro , MORIYAMA, Osamu , YAMAZAKI, Iwao , CHIYONOBU, Akihiro
IPC分类号： G11C29/12 , H01L25/065 , G01R31/3185 , G01R31/3177 , G11C29/32
CPC分类号： G01R31/3177 , G01R31/318505 , G01R31/318513 , G11C29/1201 , G11C29/32 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

4. 发明公开

EP3037833A3 TEST CIRCUIT AND METHOD OF CONTROLLING TEST CIRCUIT 有权
标题翻译：测试电路和控制测试电路的方法
公开(公告)号：EP3037833A3
公开(公告)日：2016-07-27
申请号：EP15192467.7
申请日：2015-10-30
申请人： FUJITSU LIMITED
发明人： OSHIYAMA, Gen , MORIYAMA, Osamu , SHIKIBU, Takahiro , CHIYONOBU, Akihiro , YAMAZAKI, Iwao
IPC分类号： G01R31/3185 , G01R31/317
摘要： A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.
摘要翻译：提供给包括多个半导体芯片的半导体器件的测试电路包括：提供给第一芯片的测试时钟端子; 多个时钟路径，设置在所述第一芯片和第二芯片之间，通过所述第二芯片，所述测试时钟从所述第一芯片传输到所述第二芯片; 提供给第二芯片的测试单元，用于通过使用发送到第二芯片的测试时钟来测试第二芯片; 时钟检测单元，被提供给所述第二芯片，并且检测通过所述多个时钟路径中的每个时钟路径接收到的测试时钟; 以及时钟路径选择单元，被提供给第二芯片，选择多个时钟路径中的第一时钟路径作为测试时钟路径，并且将通过测试时钟路径发送的测试时钟提供给测试单元。

5. 发明公开

EP3037833A2 TEST CIRCUIT AND METHOD OF CONTROLLING TEST CIRCUIT 有权
标题翻译：测试电路及其控制方法测试电路
公开(公告)号：EP3037833A2
公开(公告)日：2016-06-29
申请号：EP15192467.7
申请日：2015-10-30
申请人： FUJITSU LIMITED
发明人： OSHIYAMA, Gen , MORIYAMA, Osamu , SHIKIBU, Takahiro , CHIYONOBU, Akihiro , YAMAZAKI, Iwao
IPC分类号： G01R31/3185 , G01R31/317
摘要： A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.

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