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1. 发明公开

EP3154060A1 APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY 有权
标题翻译：器件和方法进行有针对性的更新程序
公开(公告)号：EP3154060A1
公开(公告)日：2017-04-12
申请号：EP16200792.6
申请日：2014-01-17
申请人： Micron Technology, Inc.
发明人： JONES, William F. , WRIGHT, Jeffrey P.
IPC分类号： G11C11/406 , G11C11/408 , G11C11/401 , G11C8/10 , G11C29/00
CPC分类号： G11C8/10 , G11C11/406 , G11C11/40611 , G11C11/40622 , G11C11/4087 , G11C17/16 , G11C17/18 , G11C29/783 , G11C2211/4068
摘要： Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

2. 发明公开

EP3279899A4 DRAM REFRESHING METHOD, APPARATUS AND SYSTEM 有权
公开(公告)号：EP3279899A4
公开(公告)日：2018-03-28
申请号：EP15891059
申请日：2015-05-04
申请人： HUAWEI TECH CO LTD
发明人： XIAO SHIHAI , HUANG YONGBING , HE RUI
IPC分类号： G11C11/406 , G11C11/403
CPC分类号： G11C29/783 , G11C11/403 , G11C11/406 , G11C11/40607 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C11/4091
摘要： A DRAM refresh method, apparatus, and system are provided. A to-be-refreshed area in a refresh block is specified in a refresh instruction, so as to refresh a specified location of a DRAM storage array. The method includes: receiving, by a DRAM refresh apparatus, a refresh instruction from a memory controller, where the refresh instruction includes an identifier of a to-be-refreshed block and refresh information used to indicate a to-be-refreshed area, and the refresh instruction is used to instruct the DRAM refresh apparatus to refresh the to-be-refreshed area in the to-be-refreshed block (S902); generating, by the DRAM refresh apparatus, addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information (S904); and refreshing, by the DRAM refresh apparatus, locations corresponding to the addresses of the bank rows in the to-be-refreshed block (S906). In this way, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

3. 发明公开

EP3087488A4 INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR 有权
公开(公告)号：EP3087488A4
公开(公告)日：2017-12-06
申请号：EP14873755
申请日：2014-12-22
申请人： INTEL CORP
发明人： QUERBACH BRUCE , SCHOENBORN THEODORE Z , ZIMMERMAN DAVID J , ELLIS DAVID G , HAMPSON CHRISTOPHER W , WAN IFAR , ZHANG YULAN , MALLELA RAMAKRISHNA , LUI WILLIAM K
IPC分类号： G11C29/36 , G11C11/406 , G11C29/00 , G11C29/10 , G11C29/12 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/44
CPC分类号： G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
摘要： In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

4. 发明公开

EP3195320A2 METHOD AND APPARATUS FOR IN-SYSTEM REPAIR OF MEMORY IN BURST REFRESH BY REDUNDANCY ALLOCATION VIA OTP ELEMENTS 审中-公开
标题翻译：通过OTP元件通过冗余分配在系统修复内存中突发刷新的方法和设备
公开(公告)号：EP3195320A2
公开(公告)日：2017-07-26
申请号：EP15771409.8
申请日：2015-09-16
申请人： Qualcomm Incorporated
发明人： KIM, Jung Pill , CHUN, Dexter Tamio , SRIRAMAGIRI, Deepti Vijayalakshmi , SUH, Jungwon
IPC分类号： G11C29/02 , G11C11/406 , G11C17/18 , G11C29/00
CPC分类号： G11C29/78 , G06F11/073 , G06F11/0751 , G06F11/0793 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/783 , G11C29/787
摘要： In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval.
摘要翻译：在随机存取存储器（RAM）的修复中，当RAM的内容有效时，接收错误信息，识别的RAM的失效地址，以及应用于冗余电路的一部分的一次性编程。可选地，RAM是动态存取RAM（DRAM），刷新突发被施加到DRAM，随后是非刷新间隔，并且在非刷新间隔期间执行一次性编程。

5. 发明公开

EP3087488A1 INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR 有权
标题翻译： DETEKTION UND REPARATUR VON DEFEKTEN IN INTEGRIERTEN SCHALTKREISEN
公开(公告)号：EP3087488A1
公开(公告)日：2016-11-02
申请号：EP14873755.4
申请日：2014-12-22
申请人： Intel Corporation
发明人： QUERBACH, Bruce , SCHOENBORN, Theodore Z. , ZIMMERMAN, David J. , ELLIS, David G. , HAMPSON, Christopher W. , WAN, Ifar , ZHANG, Yulan , MALLELA, Ramakrishna , LUI, William K.
IPC分类号： G06F11/07 , G06F11/263
CPC分类号： G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
摘要： In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.
摘要翻译：根据本说明书，一种装置包括内部缺陷检测和修复电路，其包括内置在该装置内的自检逻辑电路和内置在该装置内的自修复逻辑电路。在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。在识别一个或多个有缺陷的存储器单元时，内建的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。在一个实施例中，作为存储器地址和周期性地址偏移的函数产生数据模式。本文描述了其它方面。

6. 发明公开

EP2951831A1 APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY 审中-公开
标题翻译： VORRICHTUNGEN UND VERFAHREN ZUR GEZIELTEN AKTUALISIERUNG EINES SPEICHERS
公开(公告)号：EP2951831A1
公开(公告)日：2015-12-09
申请号：EP14745923.4
申请日：2014-01-17
申请人： Micron Technology, Inc.
发明人： JONES, William F. , WRIGHT, Jeffrey P.
IPC分类号： G11C11/401 , G11C11/406
CPC分类号： G11C8/10 , G11C11/406 , G11C11/40611 , G11C11/40622 , G11C11/4087 , G11C17/16 , G11C17/18 , G11C29/783 , G11C2211/4068
摘要： Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
摘要翻译：本文公开了用于目标行刷新的装置和方法。在示例性装置中，预解码器接收目标行地址，并确定与目标行地址相关联的目标行存储器是主存储器还是冗余存储器行。如果主行是目标行或物理上与要刷新的存储器的冗余行物理相邻的存储器的一行或多行存储器，则该预解码器还被配置为使物理上邻近存储器主行的一行或多行存储器被刷新，内存冗余行是目标行内存。

7. 发明授权

EP1596399B1 Semiconductor memory with refresh and redundancy circuit 有权
标题翻译：半导体存储器刷新和冗余电路
公开(公告)号：EP1596399B1
公开(公告)日：2006-09-06
申请号：EP04257847.6
申请日：2004-12-16
申请人： FUJITSU LIMITED
发明人： Okuyama, Yoshiaki, Fujitsu Limited , Mori, Kaoru, Fujitsu Limited
IPC分类号： G11C11/406 , G11C29/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C29/783

8. 发明公开

EP1596399A1 Semiconductor memory with refresh and redundancy circuit 有权
标题翻译： Halbleiterspeicher mit Refresh- und Redundanzschaltungen
公开(公告)号：EP1596399A1
公开(公告)日：2005-11-16
申请号：EP04257847.6
申请日：2004-12-16
申请人： FUJITSU LIMITED
发明人： Okuyama, Yoshiaki, Fujitsu Limited , Mori, Kaoru, Fujitsu Limited
IPC分类号： G11C11/406 , G11C29/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C29/783
摘要： An arbiter (22) judges which of an internal access request and an external access request takes higher priority, when the internal access request conflicts with the external access request. A redundancy judgement circuit (28) judges which of a normal memory cell and a redundancy memory cell is accessed, in accordance with each of the internal access request and the external access request. When the arbiter (22) gives higher priority to the internal access request, the redundancy judgement circuit (28) carries out redundancy judgement for the external access request during internal access operation. To prevent the malfunction of a memory core (34), a hold circuit holds redundancy judged result, and prevents the redundancy judged result for the external access request from being transmitted to the memory core (34) that carries out the internal access operation.
摘要翻译：当内部访问请求与外部访问请求冲突时，仲裁器（22）判断哪个内部访问请求和外部访问请求具有较高优先级。根据内部访问请求和外部访问请求中的每一个，冗余判断电路（28）判断访问正常存储单元和冗余存储单元中的哪一个。当仲裁器（22）对内部访问请求给予较高优先级时，冗余判断电路（28）在内部访问操作期间对外部访问请求执行冗余判断。为了防止存储器核心（34）的故障，保持电路保持冗余判断结果，并且防止外部访问请求的冗余判断结果被发送到执行内部访问操作的存储器核心（34）。

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