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1. 发明授权

EP3229040B1 OPTOELEKTRONISCHER SENSOR MIT EINEM MESSDATENSPEICHER UND SPEICHERTESTVERFAHREN 有权转让
公开(公告)号：EP3229040B1
公开(公告)日：2019-06-12
申请号：EP17164787.8
申请日：2017-04-04
申请人： Sick AG
发明人： Schopp, Thomas
IPC分类号： G01S7/497 , G01S17/42 , G11C29/08 , G11C29/56

2. 发明公开

EP2608211A1 Method of testing a flash memory 审中-公开
标题翻译： Verfahren zum Testen使用Flash-Speichers
公开(公告)号：EP2608211A1
公开(公告)日：2013-06-26
申请号：EP11195106.7
申请日：2011-12-22
申请人： Fluiditech IP Limited
发明人： Chu, Yung-Chiang
IPC分类号： G11C29/08 , G06F11/10
CPC分类号： G11C29/08 , G11C29/88 , G11C2029/4402
摘要： A method of testing a flash memory is applied to retrieve the flash memory available by picking up a defective flash memory. The flash memory includes at least a block, a page, and a cell. The method comprises inputting a test command into the flash memory to execute at least one of write, read, or compare of the flash memory. After the test command is executed, the states of the block, page, and cell in the flash memory may be obtained. The states are marked in a flash memory distribution list to allow a controller to access at least one of the normal block, page, and cell from the list. Thus, in the method, the normal block, page, and cell may be obtained.
摘要翻译：应用测试闪存的方法以通过拾取有缺陷的闪存来检索可用的闪存。闪存至少包括块，页和单元。该方法包括将测试命令输入到闪速存储器中以执行闪速存储器的写入，读取或比较中的至少一个。在执行测试命令之后，可以获得闪速存储器中的块，页面和单元的状态。这些状态被标记在闪存分配列表中，以允许控制器从列表中访问正常块，页面和单元格中的至少一个。因此，在该方法中，可以获得正常块，页面和单元。

3. 发明授权

EP3557582B1 FAILURE DETECTION APPARATUS, FAILURE DETECTION METHOD, AND FAILURE DETECTION PROGRAM 有权
公开(公告)号：EP3557582B1
公开(公告)日：2024-10-02
申请号：EP19169194.8
申请日：2019-04-15
IPC分类号： G11C29/44 , G11C29/08 , G06F11/10
CPC分类号： G11C2029/040920130101 , G11C29/08 , G06F11/1048

4. 发明授权

EP3239984B1 METHODS AND SYSTEMS FOR ANALYZING RECORD AND USAGE IN POST PACKAGE REPAIR 有权
公开(公告)号：EP3239984B1
公开(公告)日：2020-01-01
申请号：EP17165233.2
申请日：2017-04-06
申请人： Quanta Computer Inc.
发明人： Wu, Feng-Chou
IPC分类号： G11C29/00 , G11C29/44 , G11C5/04 , G06F11/10 , G11C29/04 , G11C29/08

5. 发明公开

EP2587489A1 Systems and methods for testing memories 审中-公开
标题翻译： Systeme und Verfahren zum Testen von Speichern
公开(公告)号：EP2587489A1
公开(公告)日：2013-05-01
申请号：EP12188620.4
申请日：2012-10-16
申请人： Maishi Electronic (Shanghai) Ltd.
发明人： Zhang, Weihua , Yu, Mei
IPC分类号： G11C29/56 , G11C29/08
CPC分类号： G11C29/56004 , G11C29/08 , G11C2029/0401 , G11C2029/2602 , G11C2029/5602
摘要： A system for testing a plurality of memories includes a plurality of memory testing devices and a controller. Each of the memory testing devices is coupled to one of the memories. The controller is configured to generate a test vector and send the test vector to the memory testing devices. Each of the memory testing devices tests its coupled memory respectively according to the test vector and sends a test result to the controller.
摘要翻译：用于测试多个存储器的系统包括多个存储器测试设备和控制器。每个存储器测试设备耦合到一个存储器。控制器被配置为生成测试向量并将测试向量发送到存储器测试设备。每个内存测试设备根据测试向量分别测试其耦合的内存，并将测试结果发送给控制器。

6. 发明授权

EP1447814B1 Method and apparatus for testing embedded memory on devices with multiple processor cores 有权
标题翻译：一种用于具有多个处理器的测试嵌入式存储器件的方法和装置
公开(公告)号：EP1447814B1
公开(公告)日：2013-01-09
申请号：EP04100367.4
申请日：2004-02-02
申请人： Texas Instruments Incorporated
发明人： Jarboe Jr., James M. , Wright, Nathan W. , Schutt, Nicholas H. , Ho, Van T.
IPC分类号： G11C29/08
CPC分类号： G11C29/08

7. 发明公开

EP4322167A1 DATA INPUT VERIFICATION METHOD AND DATA INPUT VERIFICATION STRUCTURE 审中-实审
公开(公告)号：EP4322167A1
公开(公告)日：2024-02-14
申请号：EP22924578.2
申请日：2022-10-08
申请人： Changxin Memory Technologies, Inc.
发明人： LIN, Feng
IPC分类号： G11C29/08
摘要： A data input verification method and a data input verification structure are provided in the present disclosure. The data input verification method includes: generating a randomly combined input character string; generating a test input signal inputted to a receiver of a memory based on the input character string and a simulated inter-symbol interference value, where the simulated inter-symbol interference value is an estimated value of inter-symbol interference transmitted from an output end of a memory controller to the receiver; inputting the test input signal into the receiver and obtaining an output signal of the receiver; determining whether a string represented by the output signal is equal to the input string and generating an eye diagram of the output signal.

8. 发明公开

EP4138082A1 MEMORY STORAGE DEVICE, AN OPERATION METHOD OF THE MEMORY STORAGE DEVICE, TEST METHOD AND ELECTRONIC DEVICE 审中-实审
公开(公告)号：EP4138082A1
公开(公告)日：2023-02-22
申请号：EP22181361.1
申请日：2022-06-27
申请人： Samsung Electronics Co., Ltd.
发明人： HUH, Sung Oh , KANG, Young San , KIM, Soo-Hyeong , KIM, Dong Hee , CHOI, Jong Kyu
IPC分类号： G11C29/08 , G11C29/44 , G11C29/48 , G11C29/56 , G11C7/20
摘要： A memory storage device (1) that performs real-time monitoring is provided. The memory storage device (1) comprises a memory controller (200), and a status indicating module/circuit (240), wherein the memory controller (200) is configured to perform a first and a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device (1), to generate a first status parameter regarding a status of the memory storage device (1) in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device (1) in which a second initialization operation is performed. The status indicating circuit (240) includes a first transistor (TR1) configured to operate on the basis of the first status parameter, a first resistor (R1) connected to the first transistor (TR1), a second transistor (TR2) configured to operate on the basis of the second status parameter, and a second resistor (R1) connected to the second transistor (TR2).

9. 发明授权

EP3477647B1 EFFICIENT TESTING OF A MAGNETIC MEMORY CIRCUIT 有权
公开(公告)号：EP3477647B1
公开(公告)日：2022-04-27
申请号：EP17001784.2
申请日：2017-10-27
发明人： Oboril, Fabian , Bishnoi, Rajendra , Tahoori, Mehdi
IPC分类号： G11C29/08 , G11C11/16 , G11C8/14 , G11C8/08

10. 发明公开

EP3477647A1 EFFICIENT TESTING OF A MAGNETIC MEMORY CIRCUIT 有权
公开(公告)号：EP3477647A1
公开(公告)日：2019-05-01
申请号：EP17001784.2
申请日：2017-10-27
申请人： Karlsruher Institut für Technologie
发明人： Oboril, Fabian , Bishnoi, Rajendra , Tahoori, Mehdi
IPC分类号： G11C29/08 , G11C11/16 , G11C8/14 , G11C8/08
摘要： Summarizing the invention, a memory circuit is provided. The memory circuit comprises at least one bit cell comprising a magnet tunnel junction including two ferromagnetic layers and comprising three electronic switches, wherein: one ferromagnetic layer has a fixed magnetic orientation and the other ferromagnetic layer has a changeable magnetic orientation that is configured to be changed by a current flow through the ferromagnetic layer; and the three electronic switches comprise a write access electronic switch configured to control the access to the bit cell during write operations, a read access electronic switch configured to control the access to the bit cell during read operations and a read-and-write access electronic switch configured to control the access to the bit cell during both read and write operations; and comprises at least one logic circuit comprising three control pins, each pin configured to receive a single input signal, and output pins, each output pin connected to a corresponding electronic switch of the three electronic switches, wherein the three control pins comprise a test pin configured to enable or disable simultaneous read and write operations within one clock cycle. The simultaneous read and write operation is applied to a bit cell comprising three access switches and is based on that the read operation is faster than the simultaneous write operation. The previously stored data value is thus read before the writing of the new data value has possibly changed the previously stored data value.

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