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11. 发明公开

EP3029831A1 Process skew resilient digital CMOS circuit 有权
标题翻译： Verfahrensversatzflexible数字CMOS-Schaltung
公开(公告)号：EP3029831A1
公开(公告)日：2016-06-08
申请号：EP14196607.7
申请日：2014-12-05
申请人： Stichting IMEC Nederland
发明人： Gemmeke, Tobias
IPC分类号： H03K5/08 , G11C29/02 , H03K19/0185
CPC分类号： G06F1/10 , G11C29/021 , H02M3/10 , H03K5/082 , H03K5/159 , H03K19/018585
摘要： A digital CMOS circuit (20) comprising at least one pull-up circuit (21) arranged when in the on-state to switch an output node of the digital CMOS circuit from a first voltage level to a second voltage level within a rising transition delay. The digital CMOS circuit (20) comprising at least one pull-down circuit (22) arranged when on-state to switch the voltage level of the output node of the digital CMOS circuit from the second voltage level to the first voltage level within a falling transition delay. The digital CMOS circuit comprises at least one performance matching transistor (23) serially connected to the first and second type transistors, the gate terminal of which is connected to biasing means arranged for biasing the at least one performance matching transistor (23) in such a way so as to compensate the performance mismatch between the at least one first and second type transistors.
摘要翻译：一种数字CMOS电路（20），包括至少一个上拉电路（21），其处于导通状态，以将数字CMOS电路的输出节点从第一电压电平切换到升高的转变延迟内的第二电压电平。所述数字CMOS电路（20）包括至少一个下拉电路（22），所述至少一个下拉电路（22）在导通状态时被布置，以将所述数字CMOS电路的输出节点的电压电平从所述第二电压电平切换到所述第一电压电平转换延迟。数字CMOS电路包括串联连接到第一和第二类型晶体管的至少一个性能匹配晶体管（23），其栅极端子被连接到偏置装置，偏置装置被布置成用于将至少一个性能匹配晶体管（23）偏置在这样的以便补偿所述至少一个第一和第二类型晶体管之间的性能失配。

12. 发明公开

EP2913929A3 LC lattice delay line for high-speed ADC applications 审中-公开
标题翻译：快速ADC应用LC-格延迟线
公开(公告)号：EP2913929A3
公开(公告)日：2016-03-02
申请号：EP15156825.0
申请日：2015-02-26
申请人： Analog Devices Global
发明人： Dong, Yunzhi , Li, Zhao , Schreier, Richard E. , Shibata, Hajime , Caldwell, Trevor Clifford
IPC分类号： H03M1/14 , H03K5/159 , H03M1/06 , H03M3/00
CPC分类号： H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
摘要： This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

13. 发明公开

EP2499741A1 TIME-TO-DIGITAL CONVERTER WITH SUCCESSIVE MEASUREMENTS 有权
标题翻译：与连续测量时间数字转换器
公开(公告)号：EP2499741A1
公开(公告)日：2012-09-19
申请号：EP10781483.2
申请日：2010-11-12
申请人： ST-Ericsson SA
发明人： RIEUBON, Sébastien
IPC分类号： H03K5/159
CPC分类号： H03K5/159
摘要： The invention relates to the conversion into digital information of the time difference between a first signal and a second signal. In particular, in order to determine a fractional part of the number of periods of a first signal for a period of a second signal, the following are alternately performed: /1/ delaying the second signal relative to the first signal and determining a first digital information item, a function of the fractional part, /2/ delaying the first signal relative to the second signal and determining a second digital information item, a function of the fractional part. Then the fractional part is calculated as a function of the previously obtained first and second digital information items.

14. 发明公开

EP1402641A2 METHOD AND APPARATUS FOR A CLOCK CIRCUIT 有权
标题翻译：方法和装置时钟电路
公开(公告)号：EP1402641A2
公开(公告)日：2004-03-31
申请号：EP02737453.7
申请日：2002-05-07
申请人： MOTOROLA, INC.
发明人： MOSHE, David , GUTKING, Eyal , DINO, Shmuel , TOZIK, Maksim
IPC分类号： H03L7/081
CPC分类号： H03L7/0805 , G06F1/10 , G11C7/1072 , G11C7/222 , H03K5/159 , H03K2005/00286 , H03L7/0814
摘要： An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.

15. 发明公开

EP1278307A2 Circuit and method for correcting clock duty cycle 审中-公开
标题翻译： Schaltung und Verfahren zur Korrektur desTastverhältnisseseines Taktsignals
公开(公告)号：EP1278307A2
公开(公告)日：2003-01-22
申请号：EP02253693.2
申请日：2002-05-27
申请人： Nokia Corporation
发明人： Heikkila, Juha M.
IPC分类号： H03L7/00 , H03K5/156
CPC分类号： H03K5/00006 , H03K5/1565 , H03K5/159 , H03L7/0812 , H04L7/0008 , H04L7/0037
摘要： Disclosed is a circuit for controlling the duty cycle and jitter of a clock signal. The circuit has an input node for receiving the clock signal and an output node for outputting a processed clock signal having a first edge that is synchronized to an edge of the clock signal and a second edge that is varied so as to provide a predetermined processed clock signal duty cycle. The predetermined duty cycle is preferably a 50-50 duty cycle. The output node may be coupled to baseband circuitry of a wireless communications terminal, such as a cellular telephone. The circuit is constructed to include a plurality of serially connected delay elements that are coupled to the clock signal at the input node. The plurality of delay elements together introduce a nominal one cycle delay into the clock signal. The circuit also includes a phase detector having a first input signal coupled to the clock signal and a second input coupled to an output of the plurality of delay elements for receiving a delayed clock signal therefrom. The phase detector operates so as to generate an error signal that is indicative of a phase difference between the clock signal and the delayed clock signal. The error signal is coupled to at least one of the delay elements for controlling the delay element for minimizing the phase difference between the clock signal and the delayed clock signal. The circuit also includes a first divider circuit having an input coupled to the clock signal, a second divider circuit having an input coupled to an output of a first one of the plurality of delay elements for receiving a one half cycle delayed clock signal therefrom, and a gate having inputs coupled to outputs of the first and second divider circuits and an output coupled to the output node for outputting the processed clock signal.
摘要翻译：公开了一种用于控制时钟信号的占空比和抖动的电路。电路具有用于接收时钟信号的输入节点和用于输出经处理的时钟信号的输出节点，该处理时钟信号具有与时钟信号的边沿同步的第一边沿，第二边缘被改变以提供预定的处理时钟信号占空比。预定占空比优选为50-50占空比。输出节点可以耦合到诸如蜂窝电话的无线通信终端的基带电路。电路被构造为包括多个串联连接的延迟元件，其被连接到输入节点处的时钟信号。多个延迟元件一起在时钟信号中引入标称的一个周期延迟。该电路还包括具有耦合到时钟信号的第一输入信号和耦合到多个延迟元件的输出的第二输入的相位检测器，用于从其接收延迟的时钟信号。相位检测器操作以产生指示时钟信号和延迟的时钟信号之间的相位差的误差信号。误差信号耦合到至少一个延迟元件，用于控制延迟元件，以使时钟信号和延迟的时钟信号之间的相位差最小化。电路还包括具有耦合到时钟信号的输入的第一分频器电路，第二分频器电路具有耦合到多个延迟元件中的第一个延迟元件的第一个的输出的输入端，用于从其接收一个半周期延迟的时钟信号;以及具有耦合到所述第一和第二除法器电路的输出的输入的栅极和耦合到所述输出节点的用于输出所处理的时钟信号的输出。

16. 发明公开

EP3407355A1 MEMORY SYSTEM WITH LOW READ POWER 有权
公开(公告)号：EP3407355A1
公开(公告)日：2018-11-28
申请号：EP17177772.5
申请日：2017-06-26
申请人： eMemory Technology Inc.
发明人： Wu, Po-Ching
IPC分类号： G11C7/06 , G11C7/14 , G11C29/00 , G11C16/28 , G11C13/00
CPC分类号： G11C7/065 , G11C5/145 , G11C5/147 , G11C7/06 , G11C7/062 , G11C7/12 , G11C7/14 , G11C7/18 , G11C7/22 , G11C11/419 , G11C16/28 , G11C17/165 , G11C17/18 , G11C29/78 , G11C2013/0042 , G11C2207/002 , G11C2207/005 , G11C2211/4013 , H01L23/5252 , H01L27/11206 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/42376 , H01L29/7848 , H01L29/7851 , H02M3/07 , H02M2003/075 , H03K3/012 , H03K5/134 , H03K5/159 , H03K17/687 , H03K2005/00195
摘要： A memory system (10) with low read power includes a first memory bank (MBA), a first path selector (YP1), a second memory bank (MBB), a second path selector (YP2), and a sensing device (100). The first path selector (YP1) is coupled to the memory cells in the first memory bank (MBA) through a plurality of first bit lines (BLA1 to BLAN). The second path selector (YP2) is coupled to the second memory cells in the second memory bank (MBB) through a plurality of second bit lines (BLB1 to BLBN). The sensing device (100) is coupled to the output terminals of the first bank selector (YP1) and the second bank selector (YP2). By sharing the sensing device (100) to sense the read currents of the corresponding memory cells, the memory system (10) is able to perform read operation with low power.

17. 发明公开

EP3146622A4 FEED-FORWARD BIAS CIRCUIT 有权
公开(公告)号：EP3146622A4
公开(公告)日：2018-05-02
申请号：EP14892709
申请日：2014-05-23
申请人： QUALCOMM INC
发明人： SU WENJUN , LEE CHULKYU , ZHANG LE , YIN GUANGMING
IPC分类号： G05F3/20 , G05F3/24 , G05F3/26 , H03K3/011 , H03K5/159 , H03K17/14 , H03K19/003
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

18. 发明公开

EP3242397A1 STRUCTURE DE MULTIPLEXEUR 审中-实审
标题翻译：多路复用器结构
公开(公告)号：EP3242397A1
公开(公告)日：2017-11-08
申请号：EP16198958.7
申请日：2016-11-15
申请人： STMICROELECTRONICS (ROUSSET) SAS
发明人： MARTINEZ, Albert , AGOYAN, Michel
IPC分类号： H03K3/84 , G06F7/58 , H03K19/173
CPC分类号： H03K17/005 , G06F7/58 , H03K3/84 , H03K5/159 , H03K19/003 , H03K19/1737
摘要： L'invention concerne un multiplexeur logique (7), deux vers un, comportant : deux bornes d'entrée (A, B) ; une borne de sortie (Z) ; une borne de commande (S) ; et un multiple de quatre multiplexeurs unitaires deux vers un (72, 74, 76, 78) raccordés en série, un premier multiplexeur unitaire (72) ayant ses entrées connectées aux bornes d'entrée, un dernier multiplexeur unitaire (78) ayant sa sortie connectée à la borne de sortie et les autres multiplexeurs unitaires (74, 76) ayant leurs entrées respectives interconnectées à la sortie du multiplexeur précédent dans l'association en série, une moitié des multiplexeurs unitaires étant commandée en inverse (75) par rapport à une autre moitié.
摘要翻译：本发明涉及一种二对一逻辑多路复用器（7），包括：两个输入端（A，B）; 输出端子（Z）; 控制终端（S）; 和的四个串联连接的，以两个单位多路复用器（72，74，76，78）的倍数时，第一多路复用器单元（72），其具有其输入端连接到输入端子，一个具有其最终输出多路复用器单元（78）连接到互连以在串联连接的最后一个多路复用器的输出的输出端，和具有各自的输入端的另一单元的多路复用器（74，76），多路复用器单元的一半是相对于控制在相反的（75）至一个另一半。

19. 发明公开

EP3055781A4 METHOD AND SYSTEM FOR CONTROLLING CIRCUIT INPUT-OUTPUT TIMING 审中-公开
标题翻译： VERFAHREN UND SYSTEM ZUR KONTROLLE EINES SCHALTKREIS-EINGANGS / AUSGANGS-TIMINGS
公开(公告)号：EP3055781A4
公开(公告)日：2017-06-28
申请号：EP14853011
申请日：2014-09-29
申请人： TEXAS INSTRUMENTS INC
发明人： TIWARI ASHUTOSH , DHAM ISH KUMAR , MURTHY PRANAV , BANSAL VIRENDRA BRIJLAL
IPC分类号： G06F13/42 , H03K5/131
CPC分类号： H03K5/159 , H03K5/131

20. 发明公开

EP3012976A3 TIMING CONTROL WITH BODY-BIAS 有权
标题翻译：时序体佩
公开(公告)号：EP3012976A3
公开(公告)日：2016-08-03
申请号：EP15186307.3
申请日：2015-09-22
申请人： NXP B.V.
发明人： SHARMA, Vibhu , KAPOOR, Ajay , MALZAHN, Ralf
IPC分类号： H03K5/159 , H03K19/094
CPC分类号： G06F1/10 , H03K5/159 , H03K19/094
摘要： Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

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