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1. 发明公开

EP3322095A1 TRISTATE AND CROSS CURRENT FREE OUTPUT BUFFER 有权
标题翻译： TRISTATE和交叉电流自由输出缓冲器
公开(公告)号：EP3322095A1
公开(公告)日：2018-05-16
申请号：EP17200919.3
申请日：2017-11-09
申请人： Tesat Spacecom GmbH & Co. KG
发明人： LÜCK, Volker
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： H04B1/74 , H03K19/003 , H03K19/00338 , H03K19/00392 , H03K19/007 , H03K19/0185 , H03K19/018521 , H03K19/094 , H03K19/09429 , H03K19/23 , H04B7/18515
摘要： A tristate output buffer (10) is provided which comprises a first branch (11) with a first buffer (110) and a second branch (12) with a second buffer (120). The first buffer (110) comprises: a supply port (Vdd), a ground port (Vss), an output port (Outa), two switchable semiconductor elements (Q1, Q1e) of a first type and two switchable semiconductor elements (Q2, Q2e) of a second type, wherein a switching behavior of the switchable semiconductor elements (Q1, Q1e) of the first type differs from a switching behavior of the switchable semiconductor elements (Q2, Q2e) of the second type, wherein the two switchable semiconductor elements (Q1, Q1e) of the first type are connected in series and are arranged between the supply port (Vdd) and the output port (Outa) such that they can be put in a conductive state independent of each other, and wherein the two switchable semiconductor elements (Q2, Q2e) of the second type are connected in series and are arranged between the ground port (Vss) and the output port (Outa) such that they can be put in a conductive state independent of each other.
摘要翻译：提供三态输出缓冲器（10），其包括具有第一缓冲器（110）的第一分支（11）和具有第二缓冲器（120）的第二分支（12）。第一缓冲器（110）包括：第一类型的两个可切换半导体元件（Q1，Q1e）和两个可切换半导体元件（Q2， Q2e），其中第一类型的可切换半导体元件（Q1，Q1e）的切换行为不同于第二类型切换半导体元件（Q2，Q2e）的切换行为，其中两个可切换半导体元件第一类型的元件（Q1，Q1e）串联连接并且布置在供应端口（Vdd）和输出端口（Outa）之间，使得它们能够彼此独立地处于导电状态，并且其中两个第二类型的可切换半导体元件（Q2，Q2e）串联连接并且布置在接地端口（Vss）和输出端口（Outa）之间，使得它们能够彼此独立地处于导通状态。

2. 发明公开

EP2983103A1 INTEGRATED CIRCUIT WITH DISTRIBUTED CLOCK TAMPERING DETECTORS 有权
标题翻译：集成电路与分布式时钟篡改探测器
公开(公告)号：EP2983103A1
公开(公告)日：2016-02-10
申请号：EP15177804.0
申请日：2015-07-22
申请人： EM Microelectronic-Marin SA
发明人： Walter, Fabrice
IPC分类号： G06F21/55 , G06F21/75
CPC分类号： G01R31/31727 , G01R31/31719 , G06F21/554 , G06F21/75 , H03K19/003
摘要： A circuit configuration for secure application includes several internal frequency detectors (10) arranged in digital units at critical points of an integrated circuit (30). The clock detectors (10) are concealed in the digital part of the integrated circuit (30) each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors (10) are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.
摘要翻译：用于安全应用的电路配置包括在集成电路（30）的关键点处以数字单元布置的多个内部频率检测器（10）。时钟检测器（10）隐藏在集成电路（30）的数字部分中，每个都作为标准单元（触发器单元），以防止任何外部操作并且隐藏其功能。时钟检测器（10）优选地布置在时钟树拓扑中，该时钟树拓扑可以处于几个级别，用于在关键点处通过不同的数字单元树来分配时钟信号。如果在任何级别监测到外部时钟攻击，则通过时钟检测器网络生成警报。

3. 发明公开

EP2917864A4 COLCKED CHARGE DOMAIN LOGIC 无效
标题翻译： COLCKED-CHARGE域逻辑
公开(公告)号：EP2917864A4
公开(公告)日：2016-01-13
申请号：EP13854026
申请日：2013-10-30
申请人： CHAOLOGIX INC
发明人： YANNETTE DANIEL F , MYERS BRENT ARNOLD
IPC分类号： G06F21/00 , G06F21/75 , G09C1/00 , H03K19/003 , H03K19/177 , H04L9/00
CPC分类号： H03K19/003 , G06F21/75 , G09C1/00 , H03K19/17768 , H04L9/003 , H04L2209/12

4. 发明授权

EP2033315B1 ELEMENT CONTROLLER FOR A RESILIENT INTEGRATED CIRCUIT ARCHITECTURE 有权
标题翻译：元件控制于柔性英格trated电路
公开(公告)号：EP2033315B1
公开(公告)日：2013-11-27
申请号：EP07796285.0
申请日：2007-06-20
申请人： Element CXI, LLC
发明人： KELEM, Steven, Hennick , BOX, Brian, A.
IPC分类号： G01R31/28 , G06F15/78 , G06F9/38 , H03K19/177
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

5. 发明公开

EP2665225A1 BIT GENERATION DEVICE AND BIT GENERATION METHOD 有权
标题翻译： BIT发电装置和位的产生方法
公开(公告)号：EP2665225A1
公开(公告)日：2013-11-20
申请号：EP11855851.9
申请日：2011-01-13
申请人： Mitsubishi Electric Corporation
发明人： SHIMIZU, Koichi , SUZUKI, Daisuke , KASUYA, Tomomi
IPC分类号： H04L9/10
CPC分类号： H03K3/02 , G09C1/00 , H03K5/1252 , H03K19/003 , H03K19/00361 , H04L9/3278
摘要： A bit generation apparatus 100 is provided with a glitch generation circuit 120 that generates glitch signals y1 to yM which include a plurality of pulses, and T-FF bit generation circuits 131(1) to 131(M) which input the glitch signals y1 to yM, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits 131(1) to 131(M) generates a respective bit value b1 to bM based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits 131(1) to 131(M), circuits that are conventionally required but not essential for the glitch PUF become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit 100.

6. 发明授权

EP2343806B1 Procédé et dispositif de contremesure pour protéger des données circulant dans un composant électronique 有权
标题翻译：在电子电路的方法和电路，用于反防御用于数据保护
公开(公告)号：EP2343806B1
公开(公告)日：2012-07-18
申请号：EP10015368.3
申请日：2010-12-07
申请人： STMicroelectronics Rousset SAS
发明人： Bancel, Frédéric , Roquelaure, Philippe
IPC分类号： H03K19/003
CPC分类号： H03K19/003

7. 发明公开

EP2145388A1 FIVE VOLT TOLERANT INTEGRATED CIRCUIT SIGNAL PAD WITH THREE VOLT ASSIST 有权
标题翻译： 5-VOLT-TOLERANTES SIGNALPADFÜREINEN INTEGRIERTEN SCHALTKREIS MIT 3-VOLT-UNTERSTÜTZUNG
公开(公告)号：EP2145388A1
公开(公告)日：2010-01-20
申请号：EP08755376.4
申请日：2008-05-13
申请人： Microchip Technology Incorporated
发明人： WANG, Guoli , THOMSEN, Joseph, A. , COOPER, Russell, E.
IPC分类号： H03K19/003
CPC分类号： H03K19/018571 , H03K19/003 , H03K19/00315
摘要： A five volt tolerant integrated circuit signal pad having an initial fast pull-up to three volts and then operating as an open drain output with an external resistor for pulling up the output from about three volts to about five volts. The initial fast (active) pull-up is accomplished with active devices that reduces the overall pull-up time of a newer technology (lower operating voltage) integrated circuit output when transitioning from a logic 0 to a logic 1. Circuits of the integrated circuit output driver protect the internal operating circuit nodes from excessive voltage and leakage currents that would otherwise result from a voltage on the signal pad that is more positive than the operating voltage of the integrated circuit.
摘要翻译：一个五伏容积的集成电路信号焊盘，其初始快速上拉至三伏，然后用外部电阻器作为开漏输出工作，将输出从约三伏提升到约五伏。初始快速（有源）上拉是通过有源器件实现的，当从逻辑0转换到逻辑1时，有源器件可以降低新技术（较低工作电压）集成电路输出的总上拉时间。集成电路的电路输出驱动器保护内部操作电路节点不受过度的电压和漏电流的影响，否则会由于信号焊盘上的电压而导致的电压和漏电流比集成电路的工作电压更正。

8. 发明公开

EP2033315A2 ELEMENT CONTROLLER FOR A RESILIENT INTEGRATED CIRCUIT ARCHITECTURE 有权
标题翻译：元件控制于柔性英格trated电路
公开(公告)号：EP2033315A2
公开(公告)日：2009-03-11
申请号：EP07796285.0
申请日：2007-06-20
申请人： Element CXI, LLC
发明人： KELEM, Steven, Hennick , BOX, Brian, A.
IPC分类号： H03K19/177
CPC分类号： G06F9/5083 , G06F9/4881 , G06F15/17362 , G06F15/7867 , G06F17/5077 , H03K19/003 , H03K19/007 , H03K19/173 , H03K19/17748 , H03K19/17764 , Y02D10/12 , Y02D10/13
摘要： The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

9. 发明公开

EP1928092A3 Semiconductor apparatus 审中-公开
公开(公告)号：EP1928092A3
公开(公告)日：2009-01-14
申请号：EP07122075.0
申请日：2007-12-03
申请人： Panasonic Corporation
发明人： Mochizuki, Kouji c/o Matsushita Electric Industrial Co.,Ltd.
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/003 , G01K7/425 , H03K19/00384
摘要： A semiconductor apparatus that is effective for problems of local characteristic variations and that enables higher speed and lower power consumption. Semiconductor apparatus (100) has: a plurality of sensor circuits (101a) to (101g) which are arranged evenly inside semiconductor apparatus (100) and detect local characteristic variations at their respective positions as delay information; and output interface circuit (102) which collects delay information detected by a plurality of sensor circuits (101a) to (101g) and outputs the collected information to outside, and, in addition, externally, has: arithmetic operating section (110) which processes detected delay information statistically and generates a control code by judging conditions such as variations in the manufacturing process; output voltage controlling section (120) which determines the voltage to be outputted using a control code recorded in non-volatile memory (103); and power supply voltage generating section (130) which supplies power supply voltage (131a) and ground potential 131b to semiconductor apparatus (100).

10. 发明授权

EP1184983B1 Interface latch for data level transfer 有权
标题翻译：用于数据传输的接口电平锁定
公开(公告)号：EP1184983B1
公开(公告)日：2007-12-12
申请号：EP00830595.5
申请日：2000-08-31
申请人： STMicroelectronics S.r.l.
发明人： Adduci, Francesco , Bona, Claudio , Fassina, Andrea
IPC分类号： H03K3/356 , H03K17/10 , H03K19/003 , H03K19/007
CPC分类号： H03K3/356113 , H03K3/356165 , H03K17/102 , H03K19/003 , H03K19/007

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