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1. 发明授权

EP2551744B1 Fast start up, ultra-low power bias generator for fast wake up oscillators 有权
公开(公告)号：EP2551744B1
公开(公告)日：2018-11-14
申请号：EP12176294.2
申请日：2012-07-13
申请人： NXP B.V.
发明人： Mahooti, Kevin , Gandhi, Sanket
IPC分类号： G05F3/24 , G05F3/26 , H03L3/00
CPC分类号： G05F3/242 , G05F1/10 , G05F3/26 , H03L3/00
摘要： Various embodiments relate to a bias generator including: a bias generator circuit; a master startup circuit that applies current to a first node in the bias generator circuit; a second startup circuit that applies current to additional nodes in the bias generator circuit; and a power switch that receives a power from a power supply and that provides power to the bias generator circuit, the master startup circuit, and the second startup circuit.

2. 发明公开

EP3391171A1 TEMPERATURE-COMPENSATED REFERENCE VOLTAGE GENERATOR THAT IMPRESSES CONTROLLED VOLTAGES ACROSS RESISTORS 有权
公开(公告)号：EP3391171A1
公开(公告)日：2018-10-24
申请号：EP16810538.5
申请日：2016-11-21
申请人： Qualcomm Incorporated
发明人： RASMUS, Todd Morgan
IPC分类号： G05F3/30
CPC分类号： G05F3/262 , G05F3/225 , G05F3/24 , G05F3/242 , G05F3/245 , G05F3/267 , G05F3/30
摘要： An apparatus and method for generating a temperature-compensated reference voltage are disclosed. The apparatus generates substantially equal temperature-compensated currents by controlling (through negative feedback) voltages across separate resistors through which the currents flow, respectively. Two of the temperature-compensated currents are formed by combining (e.g., summing) a complementary to absolute temperature (CTAT) current (ICTAT) and a proportional to absolute temperature (PTAT) current (IPTAT). A reference voltage VREF is produced by configuring the other the temperature-compensated current to flow through an output resistor.

3. 发明公开

EP3146622A4 FEED-FORWARD BIAS CIRCUIT 有权
公开(公告)号：EP3146622A4
公开(公告)日：2018-05-02
申请号：EP14892709
申请日：2014-05-23
申请人： QUALCOMM INC
发明人： SU WENJUN , LEE CHULKYU , ZHANG LE , YIN GUANGMING
IPC分类号： G05F3/20 , G05F3/24 , G05F3/26 , H03K3/011 , H03K5/159 , H03K17/14 , H03K19/003
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

4. 发明公开

EP3295273A1 REFERENCE VOLTAGES 审中-公开
公开(公告)号：EP3295273A1
公开(公告)日：2018-03-21
申请号：EP16723455
申请日：2016-05-11
申请人： NORDIC SEMICONDUCTOR ASA
发明人： WULFF CARSTEN , VELEZMORO FIORELLA INCHE
IPC分类号： G05F3/24 , G05F3/30
CPC分类号： G05F3/242 , G05F3/30
摘要： A voltage reference circuit comprises a voltage-controlled current source 2,8,10; a first reference metal-oxide-semiconductor field-effect transistor (MOSFET) 4 and a second reference MOSFET 6, wherein the threshold voltage of the two MOSFETs are different; a current mirror 12; and a load 18. The voltage-controlled current source generates a first current proportional to a difference between the threshold voltages of the first and second MOSFETs, and the current mirror 12 generates a second current, that is a scaled version of the first current, through the load 18 so as to produce a reference voltage. The voltage controlled current source can be an operational transconductance amplifier and the threshold voltage of the first MOSFET 4 can be higher than the threshold voltage of the second MOSFET 6. The reference transistors can be diode-connected and there may be a resistor 14 in series with the drain of the second MOSFET 6 having the lower threshold, the difference in threshold voltage being generated across the resistor. The current mirror can comprise transistors of different widths whose gates are connected to a common voltage. The load can be a resistor that is variable in steps using a digital control signal.

5. 发明授权

EP1380913B1 Régulateur de tension linéaire 有权
标题翻译：线性稳压器
公开(公告)号：EP1380913B1
公开(公告)日：2017-11-22
申请号：EP03300056.3
申请日：2003-07-09
申请人： STMICROELECTRONICS S.A.
发明人： Pons, Alexandre , Bernard, Christophe
IPC分类号： G05F1/56 , G05F3/26 , G05F3/24
CPC分类号： G05F3/242 , G05F1/56 , G05F3/247 , G05F3/262

6. 发明公开

EP2446337A4 REFERENCE VOLTAGE GENERATOR HAVING A TWO TRANSISTOR DESIGN 审中-公开
标题翻译：两个晶体管参考电压发生器
公开(公告)号：EP2446337A4
公开(公告)日：2016-05-25
申请号：EP10792717
申请日：2010-06-25
申请人： UNIV MICHIGAN
发明人： SEOK MINGOO , SYLVESTER DENNIS , BLAAUW DAVID , HANSON SCOTT , CHEN GREGORY
IPC分类号： G05F1/10 , G05F3/24
CPC分类号： G05F3/242

7. 发明授权

EP1624358B1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP1624358B1
公开(公告)日：2015-03-11
申请号：EP04731468.7
申请日：2004-05-06
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kimura, Hajime
IPC分类号： G09G3/32 , G05F3/24
CPC分类号： G09G3/3233 , G05F3/242 , G09G2300/0809 , G09G2300/0833 , G09G2300/0842 , G09G2300/0861 , G09G2310/0251 , G09G2320/0295 , G09G2320/043
摘要： A semiconductor device in which a transistor can supply an accurate current to a load (EL pixel and signal line) without being influenced by variations is provided. A voltage at each terminal of a transistor is adjusted by a feedback circuit using an amplifier circuit. A current Idata is input from a current source circuit to the transistor, and a gate-source voltage is set by the feedback circuit so that the transistor can flow the current Idata. The feedback circuit controls the transistor to operate in a saturation region. Thus, a gate voltage required for flowing the current Idata is set. With the use of the set transistor, a current can be supplied to a load (EL pixel and signal line) with accuracy. Note that a desired gate voltage can be set quickly since the amplifier circuit is utilized.

8. 发明公开

EP2706426A2 Low-power resistor-less voltage reference circuit 审中-公开
标题翻译： Widerstandslose Niederspannungs-Referenzschaltung
公开(公告)号：EP2706426A2
公开(公告)日：2014-03-12
申请号：EP13182995.4
申请日：2013-09-04
申请人： NXP B.V.
发明人： Gunther, Andre , Mahooti, Kevin
IPC分类号： G05F3/24 , G05F3/30
CPC分类号： G05F3/242 , G05F3/30
摘要： A method for generating a reference voltage is disclosed. The method includes generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor. The first pseudo resistor includes a transistor. The method also includes converting the PTAT voltage to a current based on a resistance of the first pseudo resistor. The method also includes mirroring the current using a current mirror circuit and converting the mirrored current to the PTAT voltage using a second pseudo resistor. The second pseudo resistor includes a transistor. The first pseudo resistor and the second pseudo resistor include equal transistor types. The method also includes generating a complimentary-to-absolute temperature (CTAT) voltage, and summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage. The resulting reference voltage is temperature independent.
摘要翻译：公开了一种用于产生参考电压的方法。该方法包括跨越第一伪电阻器产生比例绝对温度（PTAT）电压。第一伪电阻器包括晶体管。该方法还包括基于第一伪电阻器的电阻将PTAT电压转换为电流。该方法还包括使用电流镜电路对电流进行镜像，并使用第二伪电阻将镜像电流转换为PTAT电压。第二伪电阻器包括晶体管。第一伪电阻器和第二伪电阻器包括相等的晶体管类型。该方法还包括产生互补绝对温度（CTAT）电压，并将转换的PTAT电压和CTAT电压相加以产生参考电压。所得到的参考电压与温度无关。

9. 发明公开

EP2498162A1 Startup circuit for low voltage cascode beta multiplier current generator 有权
标题翻译： StartSaltungfürNiederspannungsstromgenerator eines Kaskoden-Beta-Multiplikators
公开(公告)号：EP2498162A1
公开(公告)日：2012-09-12
申请号：EP11368007.8
申请日：2011-03-07
申请人： Dialog Semiconductor GmbH
发明人： Nikolov, Ludmil , Calisto, Carlos
IPC分类号： G05F3/24
CPC分类号： G05F3/242
摘要： A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup. The second switch (196) is capable to connect the third bias voltage (164) and an inner drain-source connection (130) in the output stage of the first cascode current mirror (116) during startup.
摘要翻译：自偏置参考电路装置（100）包括第一共源共栅电流镜（116），第二共源共栅电流镜（118）和启动电路（108）。第一级联电流镜（116）能够响应于第一电流产生第一偏置电压（136）和第二偏置电压（140），并且响应于第一和第二偏置电压产生第二电流。第二共源共栅电流镜（118）能够响应于第二电流产生第三偏置电压（164），以响应于第三电流产生第四偏置电压（168），并且响应于产生第一电流到第三和第四偏置电压。启动电路包括第一开关（188）和第二开关（196）。第一开关（188）能够在启动期间连接第一偏置电压（136）和第四偏置电压（168）。第二开关（196）能够在启动期间连接第一共源共栅电流镜（116）的输出级中的第三偏置电压（164）和内部漏极 - 源极连接（130）。

10. 发明公开

EP2299429A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：EP2299429A1
公开(公告)日：2011-03-23
申请号：EP10015781.7
申请日：2004-05-06
申请人： Semiconductor Energy Laboratory Co, Ltd.
发明人： Kimura, Hajime
IPC分类号： G09G3/32 , G05F3/24
CPC分类号： G09G3/3233 , G05F3/242 , G09G2300/0809 , G09G2300/0833 , G09G2300/0842 , G09G2300/0861 , G09G2310/0251 , G09G2320/0295 , G09G2320/043
摘要： The present invention provides a semiconductor device comprising: a transistor; an amplifier circuit; and a current source circuit, wherein one of a source and a drain of the transistor is connected to the current source circuit, wherein a first input terminal of the amplifier circuit is connected to a gate of the transistor, wherein a second input terminal of the amplifier circuit is connected to the one of the source and the drain of the transistor, and wherein an output terminal of the amplifier circuit is connected to the other of the source and the drain of the transistor.
摘要翻译：本发明提供了一种半导体器件，包括：晶体管; 放大器电路; 以及电流源电路，其中所述晶体管的源极和漏极中的一个连接到所述电流源电路，其中所述放大器电路的第一输入端子连接到所述晶体管的栅极，其中所述第一输入端子放大器电路连接到晶体管的源极和漏极中的一个，并且其中放大器电路的输出端子连接到晶体管的源极和漏极中的另一个。

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