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1. 发明公开

EP4358086A1 SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT 审中-实审
公开(公告)号：EP4358086A1
公开(公告)日：2024-04-24
申请号：EP23192048.9
申请日：2023-08-18
申请人： GlobalFoundries U.S. Inc.
发明人： Chinthu, Siva Kumar , Pasupula, Suresh , Dwivedi, Devesh , Chiang, Chunsung
IPC分类号： G11C7/06 , G11C7/08 , G11C7/14 , G11C11/16 , G11C13/00
CPC分类号： G11C13/004 , G11C2013/004220130101 , G11C2013/004520130101 , G11C2013/005420130101 , G11C7/14 , G11C7/065 , G11C7/08 , G11C2207/06320130101 , G11C11/1673
摘要： Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

2. 发明授权

EP3035335B1 DIFFERENTIAL SENSING CIRCUIT WITH DYNAMIC VOLTAGE REFERENCE FOR SINGLE-ENDED BIT LINE MEMORY 有权
公开(公告)号：EP3035335B1
公开(公告)日：2018-11-21
申请号：EP15180907.6
申请日：2015-08-13
申请人： MediaTek Inc.
发明人： HUANG, Shih-Huang , HUANG, Rei-Fu
IPC分类号： G11C7/14
CPC分类号： G11C7/12 , G11C7/062 , G11C7/08 , G11C7/14 , G11C7/22
摘要： The present invention provides a differential sensing circuit (200) with a dynamic voltage reference for a single-ended bit line memory (202) is disclosed. The exemplary differential sensing circuit (200) comprises: a dynamic voltage reference generating unit (210) and a differential sensing amplifying unit (220). The dynamic voltage reference generating unit (210) is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit (220) is coupled to the single-ended bit line memory (202) and the dynamic voltage reference generating unit (210), and utilized for receiving at least an input signal from the single-ended bit line memory (202) and the dynamic voltage reference from the dynamic voltage reference generating unit (210), so as to generate at least an output signal accordingly.

3. 发明公开

EP3230984A4 APPARATUS FOR BOOSTING SOURCE-LINE VOLTAGE TO REDUCE LEAKAGE IN RESISTIVE MEMORIES 审中-公开
公开(公告)号：EP3230984A4
公开(公告)日：2018-07-04
申请号：EP15868238
申请日：2015-11-06
申请人： INTEL CORP
发明人： ARSLAN UMUT , DRAY CYRILLE
IPC分类号： G11C13/00
CPC分类号： G11C29/08 , G11C7/14 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C29/021 , G11C29/028 , G11C2029/5006
摘要： Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.

4. 发明公开

EP3252776A1 MEMORY DEVICE WITH PROGRESSIVE ROW READING AND RELATED READING METHOD 有权
标题翻译：具有逐行阅读的存储设备和相关阅读方法
公开(公告)号：EP3252776A1
公开(公告)日：2017-12-06
申请号：EP16206895.1
申请日：2016-12-23
申请人： STMicroelectronics S.r.l.
发明人： COMPARDO, Giovanni , POLIZZI, Salvatore
IPC分类号： G11C8/08 , G11C8/14 , G11C11/56 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/32 , G11C7/14 , G11C7/22 , G11C7/06
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C7/227 , G11C8/08 , G11C8/14 , G11C11/5642 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32
摘要： A memory device including: a memory array (2) with a plurality of memory cells (3) arranged in rows and columns and a plurality of word lines (WL) and bit lines (BL); a dummy structure (30) including a dummy row (38) of dummy cells and a dummy word line (WLD); a first pre-charging stage (5), which biases a word line of the memory array; an output stage (4, 10, 34, 35) including a plurality of sense amplifiers (SA 1 , SA 2 , SA 3 ), each sense amplifier generating a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage; and a second pre-charging stage (32, 36), which biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage (34), which detects a state of complete pre-charging of at least one intermediate dummy cell. A first part of the sense amplifiers (SA 1 , SA 2 ) generate the corresponding output signals following upon sensing of the state of complete pre-charging of the intermediate dummy cell.
摘要翻译：一种存储器件，包括：具有按行和列排列的多个存储器单元（3）以及多个字线（WL）和位线（BL）的存储器阵列（2）;存储器阵列包括虚拟单元的虚拟行（38）和虚拟字线（WLD）的虚拟结构（30）; 第一预充电级（5），其对存储器阵列的字线进行偏置; 包括多个读出放大器（SA1，SA2，SA3）的输出级（4,10,34,35），每个读出放大器产生表示存储在由第一预充电器充电阶段; 以及第二预充电级（32,36），其与由第一预充电级偏置的字线同时偏置伪字线。输出级包括启动级（34），其检测至少一个中间虚拟单元的完全预充电状态。感测放大器（SA1，SA2）的第一部分在感测到中间虚拟单元的完全预充电状态之后产生对应的输出信号。

5. 发明公开

EP3201924A2 CONSTANT SENSING CURRENT FOR READING RESISTIVE MEMORY 有权
标题翻译：用于读取电阻存储器的恒定电流
公开(公告)号：EP3201924A2
公开(公告)日：2017-08-09
申请号：EP15775047.2
申请日：2015-09-21
申请人： Qualcomm Incorporated , Industry-Academic Cooperation Foundation Yonsei University
发明人： JUNG, Seong-Ook , CHOI, Sara , KIM, Jisu , NA, Taehui , KIM, Jung Pill , KANG, Seung Hyuk
IPC分类号： G11C7/08 , G11C7/06 , G11C7/14 , G11C11/16 , G11C13/00
CPC分类号： G11C11/1673 , G11C7/062 , G11C7/08 , G11C7/14 , G11C13/004 , G11C2013/0045 , G11C2013/0054
摘要： Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.
摘要翻译：系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。负载电压发生器基于电流镜提供负载电压，所述电流镜被配置为提供恒定的电流，所述恒定的电流与过程电压 - 温度变化不变。通过使从恒定电流镜像的感测电流通过电阻式存储器元件，基于所产生的负载电压产生数据电压。还基于所产生的负载电压并且通过使参考电流镜像来自恒定电流而产生参考电压，通过参考单元。存储在电阻存储元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定没有过程电压 - 温度变化的影响。

6. 发明公开

EP2630643A4 REFERENCE CELL ARCHITECTURES FOR SMALL MEMORY ARRAY BLOCK ACTIVATION 有权转让
标题翻译： REFERENZZENENARCHITEKTUREN ZUR AKTIVIERUNG KLEINERSPEICHERARRAYBLÖCKE
公开(公告)号：EP2630643A4
公开(公告)日：2017-04-26
申请号：EP11834756
申请日：2011-10-20
申请人： HEADWAY TECH INC
发明人： SUNAGA TOSHIO , PU LEJAN , YUH PERG-FEI , CHANG CHAO-HUNG
IPC分类号： G11C11/16 , G11C5/06 , G11C7/14 , G11C8/12
CPC分类号： G11C5/063 , G11C7/14 , G11C8/12 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675

7. 发明授权

EP1966801B1 REFERENCE SENSE AMPLIFIER AND METHOD FOR COMPENSATED SENSING IN NON-VOLATILE MEMORY 有权
标题翻译：参考检测放大器和方法来补偿读取非易失性存储器
公开(公告)号：EP1966801B1
公开(公告)日：2016-04-20
申请号：EP06848891.5
申请日：2006-12-20
申请人： SanDisk Technologies Inc.
发明人： CHAN, Siu Lung , CERNEA, Raul-adrian
IPC分类号： G11C16/32 , G11C7/14 , G11C7/06 , G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/14 , G11C16/26 , G11C16/32 , G11C2207/063

8. 发明授权

EP2380175B1 BALANCING A SIGNAL MARGIN OF A RESISTANCE BASED MEMORY CIRCUIT 有权
标题翻译：克服了信号预留存储器电路电阻的基层
公开(公告)号：EP2380175B1
公开(公告)日：2016-03-30
申请号：EP09802075.3
申请日：2009-12-18
申请人： QUALCOMM Incorporated
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H. , YOON, Sei Seung , SANI, Mehdi Hamidi
IPC分类号： G11C11/16
CPC分类号： G11C7/14 , G11C7/12 , G11C11/1673

9. 发明公开

EP2831887A4 TRIMMABLE REFERENCE GENERATOR FOR SENSE AMPLIFIER 审中-公开
标题翻译：可调参考发生器用于传感器放大器
公开(公告)号：EP2831887A4
公开(公告)日：2015-12-23
申请号：EP13770234
申请日：2013-03-15
申请人： SILICON STORAGE TECH INC
发明人： ZHOU YAO , QIAN XIAOZHOU , YUE KAI MAN , LIN GUANGMING
IPC分类号： G11C29/00 , G11C7/14 , G11C16/26
CPC分类号： G11C16/26 , G11C7/14 , G11C16/28 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A trimmable current reference generator for use in a sense amplifier is disclosed.

10. 发明公开

EP2515305A1 Controlled value reference signal of resistance based memory circuit 有权
标题翻译：具有用于基于电阻的存储器电路的受控可变参考信号
公开(公告)号：EP2515305A1
公开(公告)日：2012-10-24
申请号：EP12176957.4
申请日：2009-06-23
申请人： Qualcomm Incorporated
发明人： Jung, Seong-Ook , Kim, Ji-Su , Song, Jee-Hwan , Kang, Seung H , Yoon, Sei Seung
IPC分类号： G11C11/16
CPC分类号： G11C7/14 , G11C11/1673 , G11C13/0002 , G11C13/004 , G11C2013/0054
摘要： A memory circuit comprises a magnetoresistive random access memory MRAM reference bit cell comprising a first current clamp and a first load circuit. The reference bit cell receives a control input at a control terminal of the first current clamp and outputs, in response to the control input, a controlled value reference voltage. The memory circuit also comprises a magnetoresistive random access memory MRAM data bit cell comprising a second load circuit, an MRAM load generator cell for generating a load control signal, the load control signal being supplied to the first load circuit and the second load circuit, and a sense amplifier. The sense amplifier comprises a first input coupled to the at least one magnetoresistive random access memory MRAM bit cell and a second input adapted to receive an input signal comprising the controlled value reference voltage.

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