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1. 发明授权

EP1333581B1 Taktsignalerzeugungseinrichtung 有权
标题翻译：时钟信号生成手段
公开(公告)号：EP1333581B1
公开(公告)日：2015-04-08
申请号：EP02002307.3
申请日：2002-01-30
申请人： Infineon Technologies AG
发明人： Steinecke, Thomas , Hesidenz, Dirk
IPC分类号： H03K5/159 , H03K7/06 , H04B15/04 , H03L7/081
CPC分类号： H03K7/06 , H03K5/159 , H03L7/081 , H04B15/04 , H04B2215/064 , H04B2215/067

2. 发明公开

EP2698926A1 Apparatus and method for generating gaussian pulse and ultra wideband communication apparatus for generating gaussian pulse 有权
标题翻译：装置和方法用于产生高斯脉冲和超宽带通信设备，用于产生高斯脉冲
公开(公告)号：EP2698926A1
公开(公告)日：2014-02-19
申请号：EP13180195.3
申请日：2013-08-13
申请人： Samsung Electronics Co., Ltd. , Tsinghua University
发明人： Geng, Shuli , Rhee, Woogeun , Kim, Jong Jin , Kim, Dong Wook , Wang, Zhihua
IPC分类号： H04B1/717 , H03K5/159 , H04L25/03
CPC分类号： H04L27/04 , H03K5/159 , H04B1/7174 , H04L25/03834
摘要： A pulse generation apparatus includes a delay pulse generator configured to generate a plurality of delay pulses, an amplitude modulator configured to modulate amplitudes of the plurality of delay pulses, and a Gaussian pulse generator configured to generate a Gaussian pulse based on the amplitude-modulated delay pulses.
摘要翻译：脉冲生成装置包括：配置为生成在配置成调制延迟脉冲的多个振幅幅度调制器延迟的脉冲的多个延迟脉冲发生器，并配置成基于所述振幅调制延迟以产生高斯脉冲的高斯脉冲发生器脉冲。

3. 发明授权

EP1488507B1 AN ARBITRARY WAVEFORM SYNTHESIZER USING A FREE-RUNNING RING OSCILLATOR 有权
标题翻译：合成器的任何信号与自由振荡式环形振荡器FORMS
公开(公告)号：EP1488507B1
公开(公告)日：2011-09-28
申请号：EP02807145.4
申请日：2002-03-25
申请人： Timelab Corporation
发明人： CARLEY, Adam, L.
IPC分类号： G06F15/00 , G06K1/00 , H04N1/40 , H04N1/46 , B41J29/38 , B41J2/205 , B41J2/045
CPC分类号： G06F1/022 , G06F1/025 , H03K5/133 , H03K5/159 , H03L7/0814 , H03L7/16
摘要： The waveform generator (100) inlcudes a free-running ring oscillator (104), an algebra module (108), a switching module (112) and an output module (114). The free-running ring oscillator (104) includes a plurality of delay elements (120p, 120o, 120c,120b, 120a) connected in a loop and a plurality of taps (TAP 15, TAP 14, TAP 2, TAP 1, TAP 0) disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module (108) generates an output signal (136) indicating a first rising edge of the arbitrary waveform in response to an input signal (132).

4. 发明公开

EP1554802A2 PULSE GENERATOR 审中-公开
标题翻译：脉冲发生器
公开(公告)号：EP1554802A2
公开(公告)日：2005-07-20
申请号：EP03808790.4
申请日：2003-09-19
申请人： Koninklijke Philips Electronics N.V.
发明人： LEENAERTS, Dominicus, M., W. , VAN DER WEIDE, Gerard
IPC分类号： H03K5/00 , H03K5/156
CPC分类号： H03K5/156 , H03K5/00006 , H03K5/06 , H03K5/159
摘要： A pulse generator comprising a series coupling of delay elements (D1, D2, D3, D4, D5) every two consecutive delay elements (D1, D2, D3, D4, D5) being coupled at a plurality of coupling points (A1, A2, A3, A4), the series coupling of delay elements (D1, D2, D3, D4, D5) having a first end (A0) and a second end (A5) coupled to a first signal (y) and a second signal (x), respectively, the first and second signals (x, y) having a same frequency and being mutually phase-shifted, the pulse generator being characterized in that it further comprises a zero-crossing detector (3) coupled to two mutually different coupling points (A2, A3) for generating an output pulse (O) having a duration determined by a ratio between a number of delay elements between the two different coupling points and a total delay of the series coupling of delay elements.

5. 发明公开

EP1278307A3 Circuit and method for correcting clock duty cycle 审中-公开
标题翻译：电路和方法，用于校正的时钟信号的占空比
公开(公告)号：EP1278307A3
公开(公告)日：2004-09-29
申请号：EP02253693.2
申请日：2002-05-27
申请人： Nokia Corporation
发明人： Heikkila, Juha M.
IPC分类号： H03L7/00 , H03K5/156
CPC分类号： H03K5/00006 , H03K5/1565 , H03K5/159 , H03L7/0812 , H04L7/0008 , H04L7/0037
摘要： Disclosed is a circuit for controlling the duty cycle and jitter of a clock signal. The circuit has an input node for receiving the clock signal and an output node for outputting a processed clock signal having a first edge that is synchronized to an edge of the clock signal and a second edge that is varied so as to provide a predetermined processed clock signal duty cycle. The predetermined duty cycle is preferably a 50-50 duty cycle. The output node may be coupled to baseband circuitry of a wireless communications terminal, such as a cellular telephone. The circuit is constructed to include a plurality of serially connected delay elements that are coupled to the clock signal at the input node. The plurality of delay elements together introduce a nominal one cycle delay into the clock signal. The circuit also includes a phase detector having a first input signal coupled to the clock signal and a second input coupled to an output of the plurality of delay elements for receiving a delayed clock signal therefrom. The phase detector operates so as to generate an error signal that is indicative of a phase difference between the clock signal and the delayed clock signal. The error signal is coupled to at least one of the delay elements for controlling the delay element for minimizing the phase difference between the clock signal and the delayed clock signal. The circuit also includes a first divider circuit having an input coupled to the clock signal, a second divider circuit having an input coupled to an output of a first one of the plurality of delay elements for receiving a one half cycle delayed clock signal therefrom, and a gate having inputs coupled to outputs of the first and second divider circuits and an output coupled to the output node for outputting the processed clock signal.

6. 发明授权

EP1237282B1 Circuit for the detection of clock signal period abnormalities 有权
标题翻译：电路，用于在一个时钟信号的检测的时间段的病症的
公开(公告)号：EP1237282B1
公开(公告)日：2003-10-08
申请号：EP02250671.1
申请日：2002-01-31
申请人： NEC Electronics Corporation
发明人： Senba, Hisanori, c/o NEC Micro Systems, Ltd.
IPC分类号： H03K21/40
CPC分类号： G01R31/31727 , H03K5/159 , H03K5/19

7. 发明公开

EP0476530A1 Apparatus for distributing clock pulses 失效
标题翻译： Vorrichtung zum Verteilung von Taktpulsen。
公开(公告)号：EP0476530A1
公开(公告)日：1992-03-25
申请号：EP91115513.3
申请日：1991-09-13
申请人： Intergraph Corporation
发明人： Herndon,William H.
IPC分类号： H03K5/15 , H03K5/159
CPC分类号： H03K5/159 , H03K5/1508
摘要： A plurality of transmission lines communicate potentially skewed clock pulses from a source of clock pulses. A combining transmission line is coupled to the plurality of transmission lines at a common node. The impedance of the combining transmission line is chosen to be substantially equal to the parallel impedances of the plurality of transmission lines to prevent reflections which degrade the clock signal. As a result, the combining transmission line combines the received clock pulses into a single clock pulse. A plurality of distribution lines are thereafter coupled to the combining transmission line at a single node. The parallel impedances of the plurality of distribution lines are chosen to be substantially equal to the impedance of the combining transmission line, once again to prevent reflections which would degrade the clock signal. The plurality of distribution lines then communicate the single clock pulses to their associated clock driven circuitry.
摘要翻译：多个传输线从时钟脉冲源传送潜在的偏斜的时钟脉冲。组合传输线在公共节点处耦合到多个传输线。选择组合传输线的阻抗基本上等于多条传输线的并联阻抗，以防止降低时钟信号的反射。结果，组合传输线将接收到的时钟脉冲组合成单个时钟脉冲。然后，多个分配线在单个节点处耦合到组合传输线。选择多个分配线的并联阻抗基本上等于组合传输线的阻抗，以再次防止会降低时钟信号的反射。然后，多个分配线将单个时钟脉冲传送到其相关联的时钟驱动电路。

8. 发明授权

EP3029831B1 Process skew resilient digital CMOS circuit 失效
公开(公告)号：EP3029831B1
公开(公告)日：2018-07-25
申请号：EP14196607.7
申请日：2014-12-05
申请人： Stichting IMEC Nederland
发明人： Gemmeke, Tobias
IPC分类号： H03K5/08 , G11C29/02 , H03K19/0185
CPC分类号： G06F1/10 , G11C29/021 , H02M3/10 , H03K5/082 , H03K5/159 , H03K19/018585
摘要： A digital CMOS circuit (20) comprising at least one pull-up circuit (21) arranged when in the on-state to switch an output node of the digital CMOS circuit from a first voltage level to a second voltage level within a rising transition delay. The digital CMOS circuit (20) comprising at least one pull-down circuit (22) arranged when on-state to switch the voltage level of the output node of the digital CMOS circuit from the second voltage level to the first voltage level within a falling transition delay. The digital CMOS circuit comprises at least one performance matching transistor (23) serially connected to the first and second type transistors, the gate terminal of which is connected to biasing means arranged for biasing the at least one performance matching transistor (23) in such a way so as to compensate the performance mismatch between the at least one first and second type transistors.

9. 发明授权

EP2698926B1 Apparatus and method for generating gaussian pulse and ultra wideband communication apparatus for generating gaussian pulse 有权
标题翻译：用于产生高斯脉冲的高斯脉冲和超宽带通信设备的设备和方法
公开(公告)号：EP2698926B1
公开(公告)日：2017-10-11
申请号：EP13180195.3
申请日：2013-08-13
申请人： Samsung Electronics Co., Ltd. , Tsinghua University
发明人： Geng, Shuli , Rhee, Woogeun , Kim, Jong Jin , Kim, Dong Wook , Wang, Zhihua
IPC分类号： H04B1/717 , H03K5/159 , H04L25/03
CPC分类号： H04L27/04 , H03K5/159 , H04B1/7174 , H04L25/03834

10. 发明公开

EP3190543A1 METHOD OF DYNAMICALLY ENCRYPTING FINGERPRINT DATA AND RELATED FINGERPRINT SENSOR 审中-公开
标题翻译：动态加密指纹数据和相关指纹传感器的方法
公开(公告)号：EP3190543A1
公开(公告)日：2017-07-12
申请号：EP16151798.2
申请日：2016-01-19
申请人： eMemory Technology Inc.
发明人： Liu, Hsin-Chou , Wang, Hung-Hsiang
IPC分类号： G06K9/00 , G06K9/60 , G06F21/32 , H04L29/06 , G06F21/60 , H04L9/32
CPC分类号： H04L63/0457 , G06F21/32 , G06F21/606 , G09C1/00 , G11C5/145 , G11C5/147 , H02M3/07 , H02M3/073 , H02M2003/075 , H03K3/012 , H03K5/1515 , H03K5/159 , H03K17/687 , H03K2005/00019 , H04L9/3231 , H04L63/0861
摘要： A dynamic encryption type fingerprint sensor (30) includes a capacitive array (38) sensing fingerprints and producing fingerprint data, an embedded non-volatile memory (eNVM) (34) storing a one-time code (OTC) (72) and an encryption algorithm indicator (74), and a logic algorithm circuit (32) encrypting the fingerprint data produced by the capacitive array (38) according to the OTC (72) and the encryption algorithm indicator (74). The logic algorithm circuit (32) includes an encryption circuit (50) having a plurality of logic encryption circuits (52,54) selected using the encryption algorithm indicator (74), the encryption circuit (50) encrypting the fingerprint data using selected logic encryption circuits (52,54) of the plurality of logic encryption circuits according to the OTC (72). A control circuit (36) is used for controlling operation of the capacitive array (38), the eNVM (34), and the logic algorithm circuit (32).
摘要翻译：动态加密型指纹传感器（30）包括感测指纹并产生指纹数据的电容阵列（38），存储一次性代码（OTC）（72）和加密的嵌入式非易失性存储器（eNVM）算法指示符（74）以及根据所述OTC（72）和所述加密算法指示符（74）对由所述电容阵列（38）产生的指纹数据进行加密的逻辑算法电路（32）。逻辑算法电路（32）包括具有使用加密算法指示符（74）选择的多个逻辑加密电路（52,54）的加密电路（50），加密电路（50）使用选择的逻辑加密来加密指纹数据根据OTC（72）的多个逻辑加密电路的电路（52,54）。控制电路（36）用于控制电容阵列（38），eNVM（34）和逻辑算法电路（32）的操作。

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