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1. 发明授权

EP2577407B1 METHOD AND APPARATUS FOR CONVERSION OF VOLTAGE VALUE TO DIGITAL WORD 有权
标题翻译：用于将电压值转换为数字字的方法和设备
公开(公告)号：EP2577407B1
公开(公告)日：2017-08-09
申请号：EP11779239.0
申请日：2011-06-05
申请人： AKADEMIA GORNICZO-HUTNICZA im. Stanislawa Staszica
发明人： KOSCIELNIK, Dariusz , MISKOWICZ, Marek
IPC分类号： H03M1/12 , H03M1/00 , H03M1/46 , H03M1/80
CPC分类号： H03M1/14 , H03M1/00 , H03M1/12 , H03M1/125 , H03M1/466 , H03M1/804

2. 发明授权

EP2953265B1 Method and circuit for bandwidth mismatch estimation in an a/d converter 有权
标题翻译：埃及A / D-Wandler的Verfahren und Schaltung zurBandbreitenfehlanpassungsschätzung
公开(公告)号：EP2953265B1
公开(公告)日：2016-12-14
申请号：EP14171580.5
申请日：2014-06-06
申请人： IMEC VZW
发明人： Deguchi, Kazuaki , Verbruggen, Bob , Craninckx, Jan
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/0604 , H03M1/00 , H03M1/002 , H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/1215 , H03M1/14 , H03M1/468 , H03M2201/4233

3. 发明公开

EP2913929A2 LC lattice delay line for high-speed ADC applications 审中-公开
标题翻译： LC-Gitter-Verzögerungsleitungfürschnelle ADC-Anwendungen
公开(公告)号：EP2913929A2
公开(公告)日：2015-09-02
申请号：EP15156825.0
申请日：2015-02-26
申请人： Analog Devices Global
发明人： Dong, Yunzhi , Li, Zhao , Schreier, Richard E. , Shibata, Hajime , Caldwell, Trevor Clifford
IPC分类号： H03M1/14
CPC分类号： H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
摘要： This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
摘要翻译：本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。具体来说，使用电感 - 电容（LC）晶格的延迟元件来实现高性能CT流水线ADC和CT delta-sigma（“£”）ADC。使用基于LC晶格的延迟元件为具有良好控制阻抗的连续时间信号提供宽带群延迟。这将是构建高性能CT ADC的重要电路部分，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

4. 发明公开

EP2577407A2 METHOD AND APPARATUS FOR CONVERSION OF VOLTAGE VALUE TO DIGITAL WORD 有权
标题翻译： VERFAHREN UND VORRICHTUNG ZUR UMWANDLUNG EINES SPANNUNGSWERTES IN EIN DIGITALES WORT
公开(公告)号：EP2577407A2
公开(公告)日：2013-04-10
申请号：EP11779239.0
申请日：2011-06-05
申请人： Akademia Gomiczo-hutnicza Im. Stanislawa Staszica
发明人： KOSCIELNIK, Dariusz , MISKOWICZ, Marek
IPC分类号： G04F10/00
CPC分类号： H03M1/14 , H03M1/00 , H03M1/12 , H03M1/125 , H03M1/466 , H03M1/804
摘要： The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-
n ) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (C
n-1 ,..., C
0 ) in the order of decreasing capacitances starting from the capacitor (C
n-1 ) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b
n-1 ,..., b
0 ) in the digital output word that correspond to the capacitors (C
n-1 ,..., C
0 ) on which the reference voltage (U
L) of a desired value has been obtained, and the value zero is assigned to the other bits.
摘要翻译：将根据本发明的将电压值转换为等于n的位数的数字字的根据本发明的解决方案的特征在于，转换的电压值首先映射到在采样电容器（Cn）中累积的一部分电荷，在触发输入（InS）的信号的有效状态下，通过使用二进制比例电容器（Cn-1，...）的阵列（A）中的电流源（I），继续重新分配累积电荷部分。（C0）以从阵列（A）中具有最高电容值的电容器（Cn-1）开始降低电容的顺序。电荷再分配的过程由控制模块（CM）基于比较器（K1）和（K2）的输出信号而不使用时钟来控制，而值1分配给这些位（bn-1 ，...，b0）对应于其上已经获得了期望值的参考电压（UL）的电容器（Cn-1，...，C0），并且分配值零到其他位。

5. 发明公开

EP2040382A4 A/D CONVERTER 有权
标题翻译：模拟 - 数字 - WANDLER
公开(公告)号：EP2040382A4
公开(公告)日：2009-08-19
申请号：EP07832891
申请日：2007-11-30
申请人： PANASONIC CORP
发明人： DOSHO SHIRO , MORIE TAKASHI , MATSUKAWA KAZUO
IPC分类号： H03M1/46 , H03M1/66 , H03M1/68
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： Provided is an A/D converter of a successive comparison type comprising a cyclic type D/A converter (11), a comparator (12) for comparing an analog value and the output value of the D/A converter (11), and storage means (13) for storing the output values of the comparator (12) sequentially to feed the stored values in the inverse order to the D/A converter (11).
摘要翻译：本发明提供一种连续比较型的A / D转换器，其包括循环型D / A转换器（11），用于比较D / A转换器（11）的模拟值和输出值的比较器（12）用于顺序地存储比较器（12）的输出值以将所存储的值以相反顺序馈送到D / A转换器（11）的装置（13）。

6. 发明公开

EP1885068A4 ANALOG/DIGITAL CONVERTER 有权
标题翻译：模拟/数字转换
公开(公告)号：EP1885068A4
公开(公告)日：2008-11-05
申请号：EP06731677
申请日：2006-04-12
申请人： FUETREK CO LTD
发明人： SUZUKI MASAHIRO
IPC分类号： H03M1/14 , H03M1/60 , H03K5/26
CPC分类号： H03M1/14 , H03M1/60
摘要： An A/D converter, which utilizes a V/F conversion, can perform an A/D conversion with high precision without raising the conversion frequency. Two VCOs are provided to utilize a difference in period therebetween, thereby determining a V/F conversion value that is shorter than the period of the main VCO. A counter (4) is used to count the pulses of a pulse signal outputted from the BASE-VCO (1), thereby generating the higher-order bits of a digital signal. On the other hand, the lower-order bits are generated by using the third register (10) and the second and third subtractors (11,12) to calculate, with respect to each sampling period, the phase difference between the beginning of the sampling period and the occurrence of the first pulse of the output of the BASE-VCO (1) within the sampling period on the basis of the number of the pulses of the output of the BASE-VCO (1) that are included in the interval between an activation of the present sampling signal (Ps) and an coincidence in phase between the output of the BASE-VCO (1) and that of the JAW-VCO (2).

7. 发明公开

EP1885068A1 ANALOG/DIGITAL CONVERTER 有权
标题翻译：模拟/数字-UMSETZER
公开(公告)号：EP1885068A1
公开(公告)日：2008-02-06
申请号：EP06731677.8
申请日：2006-04-12
申请人： Fuetrek Co. Ltd.
发明人： SUZUKI, Masahiro, c/o Fuetrek Co. Ltd.
IPC分类号： H03M1/60 , H03K5/26
CPC分类号： H03M1/14 , H03M1/60
摘要： An A-D converter utilizing V-F conversion is realized that is capable of performing A-D conversion with high precision without increasing conversion frequency. Two VCOs are provided to find a V-F conversion value that is less than a period of the main VCO by making use of a period difference between the two VCOs. By counting the number of pulses in a pulse signal that is output from a BASE-VCO 1 with a counter 4, a high order bit of a digital signal is generated. A low order bit, on the other hand, is generated by calculating, for each sampling period, a phase difference from the beginning of a sampling period until a first pulse generation in the sampling period for the output of the BASE-VCO 1 by a third register 10 and second and third subtracters 11 and 12, based on the number of pulses in the output of the BASE-VCO 1 contained in a period from a current activation time point of sampling signal Ps to a time point at which phases of outputs of the BASE-VCO 1 and JAW-VCO 2 match.
摘要翻译：实现利用V-F转换的A-D转换器，其能够在不增加转换频率的情况下以高精度执行A-D转换。提供两个VCO以通过利用两个VCO之间的周期差来找到小于主VCO的周期的V-F转换值。通过对由计数器4从BASE-VCO1输出的脉冲信号中的脉冲数进行计数，产生数字信号的高位。另一方面，通过对于每个采样周期计算从采样周期的开始到用于BASE-VCO 1的输出的采样周期中的第一脉冲产生之前的相位差，由第三寄存器10和第二和第三减法器11和12，基于从采样信号Ps的当前激活时间点到输出相位的时间段所包含的BASE-VCO1的输出中的脉冲数的BASE-VCO 1和JAW-VCO 2匹配。

8. 发明公开

EP1024348A3 Low-frequency noise removing method and a related CMOS sensing circuit 有权
标题翻译：为Niederfrequenzgerausch和CMOS电路真空方法
公开(公告)号：EP1024348A3
公开(公告)日：2004-10-13
申请号：EP99121254.9
申请日：1999-10-25
申请人： Denso Corporation
发明人： Watanabe, Takamoto , Ikuta, Toshio , Endo, Noboru
IPC分类号： G01D3/036 , G01D3/028
CPC分类号： G04F10/005 , H03M1/0619 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An intentional offset value is set beforehand. The intentional offset value is larger than a sensing objective signal "sig." A measuring device is provided for measuring the intentional offset value to obtain a measured intentional offset value "a" representing the quantity of the intentional offset value, and also for measuring a sum of the sensing objective signal "sig" and the intentional offset value to obtain a measured signal value "b" representing a summation of the quantity of the sensing objective signal and the quantity of the intentional offset value. A ratio (b/a) of the measured signal value to the measured intentional offset value is obtained. The obtained ratio is used as noise reducing data for reducing the noise involved in a sensor output.

9. 发明公开

EP0561331A2 Analog-to-digital converting circuit 失效
标题翻译： Schaltung zur Analog / / Digital-Umwandlung。
公开(公告)号：EP0561331A2
公开(公告)日：1993-09-22
申请号：EP93104187.5
申请日：1993-03-15
申请人： NIPPONDENSO CO., LTD.
发明人： Watanabe, Takamoto , Ohtsuka, Yoshinori , Hattori, Tadashi
IPC分类号： H03M1/12
CPC分类号： G04F10/005 , H03M1/0619 , H03M1/14 , H03M1/502 , H03M1/60
摘要： A pulse circulating circuit includes inverting circuits each for inverting an input signal and outputting an inversion of the input signal. A time of signal inversion by each of the inverting circuits varies in accordance with a power supply voltage applied thereto. One of the inverting circuits constitutes an inverting circuit for starting which is controllable in inversion operation. The pulse circulating circuit circulates a pulse signal therethrough after the inverting circuit for starting starts to operate. An input terminal subjected to an analog voltage signal is connected to power supply lines of the respective inverting circuits for applying the analog voltage signal to the inverting circuits as a power supply voltage fed thereto. A counter serves to count a number of times of complete circulation of the pulse signal through the pulse circulating circuit. A circulation position detecting device serves to detect a circulation position of the pulse signal in the pulse circulating circuit on the basis of output signals of the respective inverting circuits. A control device is operative for activating the inverting circuit for starting and thereby starting pulse circulating operation of the pulse circulating circuit, and for activating the circulation position detecting means at a moment which follows a moment of starting pulse circulating operation by a given time. An output device is operative for outputting digital data as an A/D conversion result. The A/D conversion result data has lower bits composed of output digital data of the circulation position detecting device, and higher bits composed of output digital data of the counter.
摘要翻译：脉冲循环电路包括用于反相输入信号并输出输入信号的反相的反相电路。每个反相电路的信号反转时间根据施加到其的电源电压而变化。反相电路中的一个构成用于启动的反相电路，其在反转操作中是可控的。脉冲循环电路在用于启动的反相电路开始运行之后循环脉冲信号。经受模拟电压信号的输入端子连接到各个反相电路的电源线，用于将模拟电压信号作为馈送到其的电源电压施加到反相电路。计数器用于通过脉冲循环电路计数脉冲信号的完整循环次数。循环位置检测装置用于根据各个反相电路的输出信号检测脉冲循环电路中的脉冲信号的循环位置。控制装置用于启动反相电路，用于启动脉冲循环电路的脉冲循环操作，从而启动循环位置检测装置，该脉冲循环位置检测装置在与给定时间开始脉冲循环操作之后的瞬间一致。输出装置用于输出数字数据作为A / D转换结果。 A / D转换结果数据具有由循环位置检测装置的输出数字数据组成的较低位，以及由计数器的输出数字数据组成的较高位。

10. 发明公开

EP0313460A1 Convertisseur analogique numérique à grande dynamique 失效
标题翻译： Analog-Digitalwandler mit hoher Dynamik。
公开(公告)号：EP0313460A1
公开(公告)日：1989-04-26
申请号：EP88402636.0
申请日：1988-10-19
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE
发明人： Poujois, Robert
IPC分类号： H03M1/60 , H03M1/52
CPC分类号： H03M1/14 , G01T1/171 , H03M1/54 , H03M1/60
摘要： Un convertisseur analogique numérique comporte des moyens (15, 16) de quantification gros et des moyens (24, 19) de quantification fins. Les moyens de quantification gros sont du type conversion courant-fréquence ou tension-fréquence à fréquence variable. Les moyens de quantification fins comportent des moyens pour mesurer la durée de décharge d'une charge résiduelle stockée dans un condensateur (3) d'intégration à l'issue de la phase de quantification grosse. Les moyens de décharge de ce condensateur comprennent un condensateur (14) de quantification de cette décharge.
摘要翻译：模拟/数字转换器包括粗略量化装置（15,16）和精细量化装置（24,19）。粗略量化装置是具有可变频率的电流/频率或电压/频率转换类型。精细量化装置包括在粗略量化相位终止时测量存储在积分电容器（3）中的残余电荷的放电时间的装置。放电该电容器的装置包括用于量化该放电的电容器（14）。 ... ...

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