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1. 发明授权

US06424199B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06424199B1
公开(公告)日：2002-07-23
申请号：US09978022
申请日：2001-10-17
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： H03K3013
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

2. 发明授权

US06509763B2 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06509763B2
公开(公告)日：2003-01-21
申请号：US10162565
申请日：2002-06-06
申请人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Hiroyoshi Tomita , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G01R1900
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

3. 发明授权

US06225841B1 Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权
公开(公告)号：US06225841B1
公开(公告)日：2001-05-01
申请号：US09556948
申请日：2000-04-21
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： H03B1900
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

4. 发明授权

US6104225A Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
标题翻译：半导体器件采用互补时钟和信号输入状态检测电路相同
公开(公告)号：US6104225A
公开(公告)日：2000-08-15
申请号：US76810
申请日：1998-05-13
申请人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
发明人： Masao Taguchi , Yasurou Matsuzaki , Miki Yanagawa
IPC分类号： G11C7/22 , H03K5/00 , H03K5/135 , H03K5/151 , H03L7/081 , G06F1/04
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/135 , H03K5/151 , H03K2005/00234 , H03L7/0814
摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.
摘要翻译：公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的系统和内部产生180°相位时钟的系统的系统。第一时钟输入电路（缓冲器）被提供有第一外部时钟并输出第一内部时钟。第二时钟输入电路（缓冲器）被提供有与第一外部时钟互补的第二外部时钟并输出第二时钟。 A + E，fra 1/2 + EE相位时钟发生电路产生与第一内部时钟异相180°的+ E，fra 1/2 + EE相移信号。第二外部时钟状态检测电路判断第二外部时钟是否被输入到第二时钟输入缓冲器。当第二外部时钟被输入时，开关被操作以产生第二时钟作为第二内部时钟，并且当第二外部时钟未被输入时产生+ E，fra 1/2 + EE相移信号作为第二内部时钟，根据第二外部时钟状态检测电路的判断。

5. 发明授权

US5929694A Semiconductor device having voltage generation circuit 失效
标题翻译：具有电压产生电路的半导体装置
公开(公告)号：US5929694A
公开(公告)日：1999-07-27
申请号：US933034
申请日：1997-09-18
申请人： Miki Yanagawa , Yasurou Matsuzaki
发明人： Miki Yanagawa , Yasurou Matsuzaki
IPC分类号： G11C11/413 , G05F3/20 , G11C5/14 , G11C8/08 , G11C11/407 , H01L21/822 , H01L27/04 , H02M3/07 , G05F1/10
CPC分类号： G11C5/143 , G05F3/205 , G11C5/145 , G11C8/08 , H02M3/073
摘要： A semiconductor device operates in one of at least two different modes including a first mode and a second mode. The semiconductor device includes a first voltage generating circuit operating in the first mode and the second mode and having a power to supply a first amount of current in order to generate a predetermined voltage level, and a second voltage generating circuit operating only in the second mode and having a power to supply a second amount of current greater than the first amount of current in order to generate the predetermined voltage level, wherein the first voltage generating circuit increases the first amount of current in the second mode compared to in the first mode.
摘要翻译：半导体器件以包括第一模式和第二模式的至少两种不同模式中的一种工作。半导体器件包括在第一模式和第二模式下工作的第一电压产生电路，并且具有供给第一电流量以产生预定电压电平的功率，以及仅在第二模式中工作的第二电压产生电路并且具有提供大于第一电流量的第二量的电流以产生预定电压电平的电力的功率，其中与第一模式相比，第一电压产生电路增加第二模式中的第一电流量。

6. 发明授权

US06498524B1 Input/output data synchronizing device 有权
标题翻译：输入/输出数据同步装置
公开(公告)号：US06498524B1
公开(公告)日：2002-12-24
申请号：US09706731
申请日：2000-11-07
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： H03L708
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

7. 发明授权

US06298004B1 Semiconductor device, semiconductor system, and digital delay circuit 失效
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US06298004B1
公开(公告)日：2001-10-02
申请号：US08892790
申请日：1997-07-15
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G11C800
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

8. 发明授权

US06185149B2 Semiconductor integrated circuit memory 有权
标题翻译：半导体集成电路存储器
公开(公告)号：US06185149B2
公开(公告)日：2001-02-06
申请号：US09340147
申请日：1999-06-28
申请人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
发明人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.
摘要翻译：半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块长度。从上述一个或多个存储单元块读取数据。

9. 发明授权

US06724675B2 Semiconductor memory device and electronic apparatus 有权
标题翻译：半导体存储器件和电子设备
公开(公告)号：US06724675B2
公开(公告)日：2004-04-20
申请号：US10352985
申请日：2003-01-29
申请人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
发明人： Akihiro Funyu , Shinya Fujioka , Hitoshi Ikeda , Takaaki Suzuki , Masao Taguchi , Kimiaki Satoh , Kotoku Sato , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/1042 , G11C7/1063 , G11C7/20 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4072
摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
摘要翻译：为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

10. 发明授权

US07782682B2 Semiconductor device with circuitry for efficient information exchange 有权
标题翻译：具有用于有效信息交换的电路的半导体器件
公开(公告)号：US07782682B2
公开(公告)日：2010-08-24
申请号：US10006238
申请日：2001-12-10
申请人： Yasurou Matsuzaki , Masao Taguchi
发明人： Yasurou Matsuzaki , Masao Taguchi
IPC分类号： G11C7/77
CPC分类号： H03M5/14 , G11C8/10 , H03M7/00 , H03M7/30
摘要： A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.
摘要翻译：具有寄存器和信息产生电路的半导体器件可以减少要传输的数据，从而节省电力。寄存器存储第一个信息。信息生成电路响应于从设备的外部获取的信号，生成指示第一信息的哪些位将被反转的第二信息。

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