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1. 发明授权

US06498524B1 Input/output data synchronizing device 有权
标题翻译：输入/输出数据同步装置
公开(公告)号：US06498524B1
公开(公告)日：2002-12-24
申请号：US09706731
申请日：2000-11-07
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： H03L708
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

2. 发明授权

US06298004B1 Semiconductor device, semiconductor system, and digital delay circuit 失效
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US06298004B1
公开(公告)日：2001-10-02
申请号：US08892790
申请日：1997-07-15
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G11C800
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

3. 发明申请

US20050242864A1 Semiconductor device, semiconductor system, and digital delay circuit 审中-公开
标题翻译：半导体器件，半导体系统和数字延迟电路
公开(公告)号：US20050242864A1
公开(公告)日：2005-11-03
申请号：US11055784
申请日：2005-02-11
申请人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
发明人： Kenichi Kawasaki , Yasuharu Sato , Terumasa Kitahara , Masao Nakano , Masao Taguchi , Yoshihiro Takemae , Yasurou Matsuzaki , Koichi Nishimura , Yoshinori Okajima , Naoharu Shinozaki , Hiroko Douchi
IPC分类号： G06F13/42 , G11C7/10 , G11C7/22 , H03H11/26 , H03K5/00 , H03K5/13 , H03L7/081
CPC分类号： G11C7/106 , G06F13/4243 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/002 , G11C2207/108 , H03K5/133 , H03K2005/00058 , H03L7/0805 , H03L7/0814
摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.
摘要翻译：公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路输出定时，使得输出信号相对于外部时钟呈现给定的相位。输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

4. 发明授权

US6028816A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 失效
公开(公告)号：US6028816A
公开(公告)日：2000-02-22
申请号：US924705
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

5. 发明授权

US6078514A Semiconductor device and semiconductor system for high-speed data transfer 失效
标题翻译：半导体器件和半导体系统，用于高速数据传输
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译：半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是沿着至少一个存储器芯片的一侧布置。

6. 发明授权

US6154405A Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data 失效
标题翻译：具有虚设单元的半导体存储器件，其将位线复位为基于在先前读取数据中读取的数据的复位电位
公开(公告)号：US6154405A
公开(公告)日：2000-11-28
申请号：US924315
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/407 , G11C11/4096 , G11C7/02
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

7. 发明授权

US06774655B2 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06774655B2
公开(公告)日：2004-08-10
申请号：US10622472
申请日：2003-07-21
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

8. 发明授权

US06621283B1 Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit 有权
标题翻译：半导体器件，半导体器件的测试方法以及半导体集成电路
公开(公告)号：US06621283B1
公开(公告)日：2003-09-16
申请号：US09437221
申请日：1999-11-10
申请人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Toshiya Uchida , Atsushi Hatakeyama , Kenichi Kawasaki , Yasuhiro Fujii
IPC分类号： G01R3102
CPC分类号： G11C29/022 , G11C29/02
摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
摘要翻译：公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

9. 发明授权

US06397312B1 Memory subsystem operated in synchronism with a clock 失效
标题翻译：内存子系统与时钟同步运行
公开(公告)号：US06397312B1
公开(公告)日：2002-05-28
申请号：US08970086
申请日：1997-11-13
申请人： Masao Nakano , Hiroyoshi Tomita , Kotoku Sato , Yoshihiro Takemae , Masao Taguchi
发明人： Masao Nakano , Hiroyoshi Tomita , Kotoku Sato , Yoshihiro Takemae , Masao Taguchi
IPC分类号： G06F1200
CPC分类号： G06F13/4243
摘要： A memory system having a simple configuration capable of high-speed data transmission is disclosed. Data is output from a controller or a memory in synchronism with a clock or a data strobe signal. The clock or the data strobe signal is transmitted by a clock signal line or a data strobe signal line, respectively, arranged in parallel to a data signal line. A delay circuit delays by a predetermined time the signals transmitted through the clock signal line or the data strobe signal line. The clock or the data strobe signal thus assumes a phase suitable for retrieval at the destination, so that the data signal can be retrieved directly by means of the received clock or the received data strobe signal.
摘要翻译：公开了一种具有能够进行高速数据传输的简单配置的存储器系统。与时钟或数据选通信号同步地从控制器或存储器输出数据。时钟或数据选通信号分别通过与数据信号线并联布置的时钟信号线或数据选通信号线来发送。延迟电路在预定时间内延迟通过时钟信号线或数据选通信号线发送的信号。因此，时钟或数据选通信号采取适合在目的地检索的相位，使得可以通过接收的时钟或接收的数据选通信号直接检索数据信号。

10. 发明授权

US06194930B1 DLL circuit 有权
标题翻译： DLL电路
公开(公告)号：US06194930B1
公开(公告)日：2001-02-27
申请号：US09320847
申请日：1999-05-26
申请人： Yasurou Matsuzaki , Masao Nakano , Yasuhiro Fujii
发明人： Yasurou Matsuzaki , Masao Nakano , Yasuhiro Fujii
IPC分类号： H03L706
CPC分类号： H03L7/0805 , H03L7/0814
摘要： The present invention is a DLL circuit, which delays a first clock, and generates a control clock having a predetermined phase relation with this first clock. The DLL circuit comprises a variable delay circuit for varying the delay of the first clock; a phase comparator for comparing the phases of the first clock against that of a second clock, generated by delaying for a predetermined time the output of the variable delay circuit, and for generating a phase comparison result signal; and a delay control circuit for supplying to the variable delay circuit a delay control signal, which controls this delay quantity in response to the phase comparison result signal. The delay control circuit generates a single delay control signal, which changes by a minimum delay quantity unit a delay quantity of the variable delay circuit in a first operating period of the DLL circuit, and generates a binary delay control signal, which changes by a binary unit a delay quantity of the variable delay circuit in a second operating period that differs from the first operating period of the DLL circuit. A lock-on state can be achieved in a short time, and stable operation is possible.
摘要翻译：本发明是一种DLL电路，其延迟第一时钟，并产生与该第一时钟具有预定相位关系的控制时钟。 DLL电路包括用于改变第一时钟的延迟的可变延迟电路; 相位比较器，用于通过将可变延迟电路的输出延迟预定时间并产生相位比较结果信号而产生的第一时钟的相位和第二时钟的相位; 以及延迟控制电路，用于向可变延迟电路提供响应于相位比较结果信号来控制该延迟量的延迟控制信号。延迟控制电路产生单个延迟控制信号，该延迟控制信号在DLL电路的第一操作周期中以最小延迟量单位改变可变延迟电路的延迟量，并产生二进制延迟控制信号，二进制延迟控制信号由二进制在与DLL电路的第一操作周期不同的第二操作周期中单元可变延迟电路的延迟量。可以在短时间内实现锁定状态，并且可以稳定地操作。

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